diff options
| author | John <john.zhao@intel.com> | 2022-03-27 09:06:25 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 16:19:36 +0000 |
| commit | 2bcc5f39c17550225840a524e875446aa05e1f6a (patch) | |
| tree | cbcf3df4c2ac1034d52c344239abe804687dac01 /src/soc/intel/common | |
| parent | 848b42558c29aca8e08564303f9a3ab8007722ac (diff) | |
soc/intel/common: Add IOE SBI access for TCSS functions
Meteor Lake has the IOE Die for TCSS. This change adds IOE SBI access
for TCSS pad configuration and Thunderbolt authentication.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/tcss.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/tcss/tcss.c | 18 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 5209858bd5..12400d8c5a 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -146,6 +146,7 @@ extern const struct soc_tcss_ops tcss_ops; /* Method to configure pads */ void tcss_configure_aux_bias_pads_regbar(const struct typec_aux_bias_pads *pads); +void ioe_tcss_configure_aux_bias_pads_sbi(const struct typec_aux_bias_pads *pads); /* * 1) Initialize TCSS muxes to disconnected state @@ -163,5 +164,6 @@ const struct tcss_port_map *tcss_get_port_info(size_t *num_ports); /* Method to validate the Thunderbolt authentication */ bool tcss_valid_tbt_auth(void); +bool ioe_tcss_valid_tbt_auth(void); #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index f1a3584400..18fff20fb2 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -368,6 +368,19 @@ void tcss_configure_aux_bias_pads_regbar( } } +void ioe_tcss_configure_aux_bias_pads_sbi( + const struct typec_aux_bias_pads *pads) +{ + for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) { + if (pads[i].pad_auxn_dc && pads[i].pad_auxp_dc) { + ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(i), + calc_bias_ctrl_reg_value(pads[i].pad_auxp_dc)); + ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(i), + calc_bias_ctrl_reg_value(pads[i].pad_auxn_dc)); + } + } +} + const struct tcss_port_map *tcss_get_port_info(size_t *num_ports) { static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; @@ -424,3 +437,8 @@ bool tcss_valid_tbt_auth(void) { return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; } + +bool ioe_tcss_valid_tbt_auth(void) +{ + return ioe_p2sb_sbi_read(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; +} |