diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-07-06 14:39:01 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-06 19:21:14 +0000 |
| commit | 22369a1fc2042868a4db009290056a266fc1b369 (patch) | |
| tree | 8b95862226267c225200b5a3c8291e1753f539ea /src/soc/intel/common | |
| parent | 8e10a4826a8fe83292a084450cf1b905ac832edd (diff) | |
soc/intel/common: Update the comment on CSE Region layout
The comment indicates CSE's data partition is placed after BP2. But, it
was place after BP1.So, the patch updates the comment to reflect the
CSE Region layout correctly.
TEST=Build the code for Brya and didn't notice any compilation errors
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index d4f474d6f1..2e8a868dc8 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -34,9 +34,9 @@ * CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are * used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT. * CSE Lite SKU Image Layout: - * ------------- ------------------- --------------------- - * |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA | - * ------------- ------------------- --------------------- + * ------------- ------------------ -------------------- + * |CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 | + * ------------- ------------------ -------------------- */ #define CSE_MAX_BOOT_PARTITIONS 3 |