diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-07 13:01:18 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-11 07:17:43 +0000 |
| commit | 05865b8fbdef5df6cda4183eb66df5ef817cfe67 (patch) | |
| tree | 3ed9d8786f2ceaa115b56e898035d4e64fbdeb70 /src/soc/intel/common | |
| parent | 17c9cfe2125736e49d335efcc624b53d213444ef (diff) | |
soc/intel/apl: Rework on CPU privilege level implementation
This patch migrates common code API into SoC specific implementation
to drop CPU privilege level as the MSR is not consistent across
platforms.
For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151.
Also, include `soc/msr.h` in cpu.h to fix the compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 3 |
3 files changed, 0 insertions, 22 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 27ff8cd151..2209b742c7 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -260,19 +260,6 @@ void cpu_set_eist(bool eist_status) } /* - * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 - * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode. - */ -void cpu_enable_untrusted_mode(void *unused) -{ - msr_t msr; - - msr = rdmsr(MSR_POWER_MISC); - msr.lo |= ENABLE_IA_UNTRUSTED; - wrmsr(MSR_POWER_MISC, msr); -} - -/* * This function fills in the number of Cores(physical) and Threads(virtual) * of the CPU in the function arguments. It also returns if the number of cores * and number of threads are equal. diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 094acebd54..3ce80b27db 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -112,12 +112,6 @@ void cpu_burst_mode(bool burst_mode_status); void cpu_set_eist(bool eist_status); /* - * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 - * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode. - */ -void cpu_enable_untrusted_mode(void *unused); - -/* * This function fills in the number of Cores(physical) and Threads(virtual) * of the CPU in the function arguments. It also returns if the number of cores * and number of threads are equal. diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e45b34dfec..41440488f4 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,9 +17,6 @@ #define MSR_BIOS_UPGD_TRIG 0x7a #define SGX_ACTIVATE_BIT (1) #define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_POWER_MISC 0x120 -#define ENABLE_IA_UNTRUSTED (1 << 6) -#define FLUSH_DL1_L2 (1 << 8) #define MSR_EMULATE_PM_TIMER 0x121 #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_PM_TMR_EN (1 << 16) |