diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-05-12 16:25:31 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-05-14 15:06:39 +0000 |
| commit | cc35f723fdcc6999ace18eae18467b900a12c07f (patch) | |
| tree | 80ee1d085e1f229b3bbcc5e1ae514a88d113240b /src/soc/intel/common | |
| parent | abd4714ee059b075be5cb94d332602a4ce454bc9 (diff) | |
soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()
This change uses cpu_phys_address_size() to calculate the size of high
MMIO region instead of a macro for each SoC. This ensures that the
entire range above TOUUD that can be addressed by the CPU is used for
MMIO above 4G boundary.
Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 7355817ec2..269236ba32 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -2,6 +2,7 @@ #include <cbmem.h> #include <console/console.h> +#include <cpu/cpu.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -102,8 +103,8 @@ void sa_fill_gnvs(global_nvs_t *gnvs) struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb); - gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; - printk(BIOS_DEBUG, "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", + gnvs->a4gs = POWER_OF_2(cpu_phys_address_size()) - gnvs->a4gb; + printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", gnvs->a4gb, gnvs->a4gs); } |