diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-06-02 12:16:04 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-05 00:21:39 +0200 |
| commit | 5391e554e190d746ae54d09cd97c313736a04027 (patch) | |
| tree | 6e6df4ebbd466fbbdb12c2e4b64aa7d560a90be4 /src/soc/intel/common | |
| parent | d86e0e6638062b5d80f5d438f0741dd735734ad4 (diff) | |
soc/intel/common/block: add bios caching to fast spi module
Add fast_spi_cache_bios_region() that sets up a variable
MTRR as write-protect covering the fast spi BIOS region.
Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 25 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/fast_spi.h | 4 |
2 files changed, 29 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 603af16881..a53499eba6 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -18,8 +18,10 @@ #include <device/pci_def.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <fast_spi_def.h> #include <intelblocks/fast_spi.h> +#include <lib.h> #include <soc/intel/common/spi_flash.h> #include <soc/pci_devs.h> #include <spi_flash.h> @@ -175,6 +177,29 @@ size_t fast_spi_get_bios_region(size_t *bios_size) return bios_start; } +void fast_spi_cache_bios_region(void) +{ + int mtrr; + size_t bios_size; + uint32_t alignment; + + mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + /* Only the IFD BIOS region is memory mapped (at top of 4G) */ + fast_spi_get_bios_region(&bios_size); + + if (!bios_size) + return; + + /* Round to power of two */ + alignment = 1 << (log2_ceil(bios_size)); + bios_size = ALIGN_UP(bios_size, alignment); + set_var_mtrr(mtrr, 4ULL*GiB - bios_size, bios_size, MTRR_TYPE_WRPROT); +} + /* * Program temporary BAR for SPI in case any of the stages before ramstage need * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index e4bddc4e45..6294001d23 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -57,6 +57,10 @@ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data); */ size_t fast_spi_get_bios_region(size_t *bios_size); /* + * Cache the memory-mapped BIOS region as write-protect type. + */ +void fast_spi_cache_bios_region(void); +/* * Program temporary BAR for FAST_SPI in case any of the stages before ramstage * need to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI * enumeration. Also, Disable the BIOS write protect and Enable Prefetching and |