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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-24 13:26:04 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-02-26 17:06:40 +0000
commit44f558ec262c671d4db76ae25eb1b8e24204d002 (patch)
treef66b2fe59486b6bcdb094822f9b57b4d09537b90 /src/soc/intel/common
parentdfd3f211740be4cf0d234bf4621ac384758a24ce (diff)
treewide: capitalize 'USB'
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/xhci/elog.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c
index 0fd41bfdf0..d8ee29c9ff 100644
--- a/src/soc/intel/common/block/xhci/elog.c
+++ b/src/soc/intel/common/block/xhci/elog.c
@@ -84,7 +84,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event)
/*
* Check if CSC bit is set and port is capable of wake on
* connect/disconnect to identify if the port caused wake
- * event for usb attach/detach.
+ * event for USB attach/detach.
*/
if (pch_xhci_csc_set(port_status) &&
pch_xhci_wake_capable(port_status)) {
@@ -95,7 +95,7 @@ static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event)
/*
* Check if PLC is set and PLS indicates resume to identify if
- * the port caused wake event for usb activity.
+ * the port caused wake event for USB activity.
*/
if (pch_xhci_plc_set(port_status) &&
pch_xhci_resume(port_status)) {