diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2019-08-31 14:54:57 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-16 07:29:36 +0000 |
| commit | d415c206b5a657f84a3ab68a272c1187dccc2e12 (patch) | |
| tree | 10453e375998cf5fab3d6bec39e7bf09f739a029 /src/soc/intel/common | |
| parent | 198f427907074767550841c8375f5cc0fae9e68c (diff) | |
src/soc/intel/{common,cnl,skl,icl}: Move global reset req function to common
send_heci_reset_req_message() is defined in multiple places,
hence move it to common code.
TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards.
Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 61 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 12 |
2 files changed, 73 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 223eab5fb2..01b20501a7 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -69,10 +69,25 @@ #define HECI_OP_MODE_SEC_OVERRIDE 5 +/* Global Reset Command ID */ +#define MKHI_GLOBAL_RESET_REQ 0xb +#define MKHI_GROUP_ID_CBM 0 + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 2 + static struct cse_device { uintptr_t sec_bar; } g_cse; +/* HECI Message Header */ +struct mkhi_hdr { + uint8_t group_id; + uint8_t command:7; + uint8_t is_resp:1; + uint8_t rsvd; + uint8_t result; +} __packed; /* * Initialize the device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been @@ -558,6 +573,52 @@ uint32_t me_read_config32(int offset) return pci_read_config32(PCH_DEV_CSE, offset); } +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/ + * HOST_RESET_ONLY/CSE_RESET_ONLY. + */ +int send_heci_reset_req_message(uint8_t rst_type) +{ + int status; + struct mkhi_hdr reply; + struct reset_message { + struct mkhi_hdr hdr; + uint8_t req_origin; + uint8_t reset_type; + } __packed; + struct reset_message msg = { + .hdr = { + .group_id = MKHI_GROUP_ID_CBM, + .command = MKHI_GLOBAL_RESET_REQ, + }, + .req_origin = GR_ORIGIN_BIOS_POST, + .reset_type = rst_type + }; + size_t reply_size; + + if (!((rst_type == GLOBAL_RESET) || + (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) + return -1; + + heci_reset(); + + reply_size = sizeof(reply); + memset(&reply, 0, reply_size); + + printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); + if (rst_type == CSE_RESET_ONLY) + status = heci_send_receive(&msg, sizeof(msg), NULL, 0); + else + status = heci_send_receive(&msg, sizeof(msg), &reply, + &reply_size); + + if (status != 1) + return -1; + + printk(BIOS_DEBUG, "HECI: Global Reset success!\n"); + return 0; +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 30d17c865a..1b08b4d4ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -106,7 +106,19 @@ void set_host_ready(void); */ uint8_t wait_cse_sec_override_mode(void); +/* + * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be + * GLOBAL_RESET/HOST_RESET_ONLY/CSE_RESET_ONLY. + * Returns -1 on failure a 0 on success. + */ +int send_heci_reset_req_message(uint8_t rst_type); + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 +/* Command GLOBAL_RESET_REQ Reset Types */ +#define GLOBAL_RESET 1 +#define HOST_RESET_ONLY 2 +#define CSE_RESET_ONLY 3 + #endif // SOC_INTEL_COMMON_MSR_H |