diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2021-04-08 20:31:47 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-21 09:19:58 +0000 |
| commit | a979460614db63212f04658a592bd883f8e28b80 (patch) | |
| tree | 288b5c44bc23c7f5cb25fd822a0f4088f5c0f865 /src/soc/intel/common | |
| parent | a50f190fd4f9392f85bbeee53114cb054ad047cc (diff) | |
soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config
is for the number of PCIe Clock sources available which is different from PCIe clock reqs.
This is more relevant in alderlake, as the number clock source and clock reqs differ.
However since this is a better name, renaming it throughout the soc/intel tree.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/pcie/rtd3/rtd3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 5a04333499..3d231b6d77 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -200,7 +200,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) __func__, scope); return; } - if (config->srcclk_pin > CONFIG_MAX_PCIE_CLOCKS) { + if (config->srcclk_pin > CONFIG_MAX_PCIE_CLOCK_SRC) { printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, config->srcclk_pin, scope); return; |