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authorElyes Haouas <ehaouas@noos.fr>2022-11-18 15:07:33 +0100
committerMartin L Roth <gaumless@gmail.com>2022-11-26 23:39:16 +0000
commit9018dee6856791ab599463a771826936c20a80bb (patch)
tree079e966e6b894bb9c81ca25e9e783c28947e0e64 /src/soc/intel/common
parent5aa98964fb4e2e8c10b1663f8d6a3faa2b700410 (diff)
src/soc/intel: Remove unnecessary space after casts
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/crashlog/crashlog.c10
-rw-r--r--src/soc/intel/common/block/cse/cse.c4
-rw-r--r--src/soc/intel/common/block/cse/cse_lite.c6
-rw-r--r--src/soc/intel/common/block/pmc/pmclib.c6
4 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c
index 239c72c058..2bdf2cc2eb 100644
--- a/src/soc/intel/common/block/crashlog/crashlog.c
+++ b/src/soc/intel/common/block/crashlog/crashlog.c
@@ -329,7 +329,7 @@ void cl_get_pmc_sram_data(void)
/* allocate mem for the record to be copied */
unsigned long pmc_cl_cbmem_addr;
- pmc_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_PMC_CRASHLOG,
+ pmc_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_PMC_CRASHLOG,
pmc_crashLog_size);
if (!pmc_cl_cbmem_addr) {
printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n");
@@ -337,7 +337,7 @@ void cl_get_pmc_sram_data(void)
}
memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size);
- dest = (u32 *)(uintptr_t) pmc_cl_cbmem_addr;
+ dest = (u32 *)(uintptr_t)pmc_cl_cbmem_addr;
bool pmc_sram = true;
pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table();
if (discovery_buf.bits.discov_mechanism == 1) {
@@ -400,16 +400,16 @@ void cl_get_cpu_sram_data(void)
/* allocate memory buffers for CPU crashog data to be copied */
unsigned long cpu_crashlog_cbmem_addr;
- cpu_crashlog_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_CPU_CRASHLOG,
+ cpu_crashlog_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_CPU_CRASHLOG,
m_cpu_crashLog_size);
if (!cpu_crashlog_cbmem_addr) {
printk(BIOS_ERR, "Failed to add CPU main crashLog entries to CBMEM.\n");
return;
}
- memset((void *) cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size);
+ memset((void *)cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size);
tmp_bar_addr = cl_get_cpu_bar_addr();
- dest = (u32 *)(uintptr_t) cpu_crashlog_cbmem_addr;
+ dest = (u32 *)(uintptr_t)cpu_crashlog_cbmem_addr;
bool pmc_sram = false;
for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) {
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index c2d44846ff..2cb3452a89 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -163,7 +163,7 @@ static size_t filled_slots(uint32_t data)
uint8_t wp, rp;
rp = data >> CSR_RP_START;
wp = data >> CSR_WP_START;
- return (uint8_t) (wp - rp);
+ return (uint8_t)(wp - rp);
}
static size_t cse_filled_slots(void)
@@ -571,7 +571,7 @@ static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen)
} while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0);
if ((hdr & MEI_HDR_IS_COMPLETE) && received) {
- *maxlen = p - (uint8_t *) buff;
+ *maxlen = p - (uint8_t *)buff;
return CSE_TX_RX_SUCCESS;
}
}
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 37640f43f6..11a4624c26 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -526,7 +526,7 @@ static bool cse_get_target_rdev(const struct cse_bp_info *cse_bp_info,
return false;
printk(BIOS_DEBUG, "cse_lite: CSE RW partition: offset = 0x%x, size = 0x%x\n",
- (uint32_t)start_offset, (uint32_t) size);
+ (uint32_t)start_offset, (uint32_t)size);
return true;
}
@@ -930,8 +930,8 @@ static void cse_sub_part_get_source_fw_version(void *subpart_cbfs_rw, struct fw_
struct subpart_entry *subpart_entry;
struct subpart_entry_manifest_header *man_hdr;
- subpart_entry = (struct subpart_entry *) (ptr + SUBPART_HEADER_SZ);
- man_hdr = (struct subpart_entry_manifest_header *) (ptr + subpart_entry->offset_bytes);
+ subpart_entry = (struct subpart_entry *)(ptr + SUBPART_HEADER_SZ);
+ man_hdr = (struct subpart_entry_manifest_header *)(ptr + subpart_entry->offset_bytes);
fw_ver->major = man_hdr->binary_version.major;
fw_ver->minor = man_hdr->binary_version.minor;
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index ea365d06d1..68bde41568 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -580,9 +580,9 @@ void pmc_gpe_init(void)
dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK;
dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK;
} else {
- gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0);
- gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1);
- gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2);
+ gpio_cfg |= (uint32_t)dw0 << GPE0_DW_SHIFT(0);
+ gpio_cfg |= (uint32_t)dw1 << GPE0_DW_SHIFT(1);
+ gpio_cfg |= (uint32_t)dw2 << GPE0_DW_SHIFT(2);
}
gpio_cfg_reg = read32p(pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;