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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-04-11 14:28:14 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-06-01 09:48:54 +0000 |
| commit | 481599f2c8c7ca8a8fb351dd198587f0e6b855bd (patch) | |
| tree | 1d6f4c118266a0f1308594239c45598267128ef8 /src/soc/intel/common | |
| parent | 29aa1e156771c7e24cefa52077f8de30f56b9d5d (diff) | |
soc/intel/fast_spi: Use smarter mtrr code in ramstage
mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It
will compute a new optimal solution with the temp ranges included
while also taking care of the cleanup before loading the payload/s3
resume.
Change-Id: I283ba07fc12c410be39dfdc828657598237247c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63550
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index c07b565d8c..ed61c10beb 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -223,6 +223,11 @@ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data) static void fast_spi_enable_cache_range(unsigned int base, unsigned int size) { + if (ENV_RAMSTAGE) { + mtrr_use_temp_range(base, size, MTRR_TYPE_WRPROT); + return; + } + const int type = MTRR_TYPE_WRPROT; int mtrr = get_free_var_mtrr(); if (mtrr == -1) { |