diff options
| author | Maximilian Brune <maximilian.brune@9elements.com> | 2023-01-04 19:22:35 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-05 12:36:29 +0000 |
| commit | 27900ea9f85f81a55246f1c27d662f92121c0563 (patch) | |
| tree | c1d93c0b29a0833bd87c50fdc15ce6c57087c9fa /src/soc/intel/common | |
| parent | 03bf97ad163bc5bcc98c6ed0af096f80a7a32127 (diff) | |
src/soc/intel: Document meaning of variables
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/meminit.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h index 3ebf5368a1..a4fb9fa1f3 100644 --- a/src/soc/intel/common/block/include/intelblocks/meminit.h +++ b/src/soc/intel/common/block/include/intelblocks/meminit.h @@ -22,8 +22,8 @@ /* Different memory topologies supported by the platform. */ enum mem_topology { - MEM_TOPO_MEMORY_DOWN = BIT(0), - MEM_TOPO_DIMM_MODULE = BIT(1), + MEM_TOPO_MEMORY_DOWN = BIT(0), // memory is soldered onto board + MEM_TOPO_DIMM_MODULE = BIT(1), // memory is composed of DIMM modules MEM_TOPO_MIXED = MEM_TOPO_MEMORY_DOWN | MEM_TOPO_DIMM_MODULE, }; diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index a4e350055e..be7c5f93f8 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -15,6 +15,7 @@ enum pcie_rp_flags { PCIE_RP_HOTPLUG = (1 << 0), + /* PCIE RP Latency Tolerance Report */ PCIE_RP_LTR = (1 << 1), /* PCIE RP Advanced Error Report */ PCIE_RP_AER = (1 << 2), |