diff options
| author | Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> | 2024-09-02 13:39:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-04 04:38:51 +0000 |
| commit | 174755f55528188ec69efe2836944c6c28e5a976 (patch) | |
| tree | 4bee983ee72be51edd09a23c7d3f395f06eb5cd1 /src/soc/intel/common | |
| parent | 2e1b7d3a151f37f90ecfc22bbe0236e1a6c918bd (diff) | |
soc/intel/common/block: Include register offsets for POWER_CTL
Details:
- Add (POWER_CTL) – Offset 0x1fc required bits.
Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 158cc9e3fe..a03032899d 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -50,7 +50,10 @@ #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_PRMRR_VALID_CONFIG 0x1fb #define MSR_POWER_CTL 0x1fc +#define ENABLE_BIDIR_PROCHOT (1 << 0) #define POWER_CTL_C1E_MASK (1 << 1) +#define PWR_PERF_PLATFORM_OVR (1 << 18) +#define VR_THERM_ALERT_DISABLE_LOCK (1 << 23) #define MSR_PRMRR_BASE_0 0x2a0 #define MSR_EVICT_CTL 0x2e0 #define MSR_LT_CONTROL 0x2e7 |