diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-04-12 13:01:02 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-04-13 07:00:27 +0200 |
| commit | ff7670915c55cfddff144e3f2d78425e0042b52a (patch) | |
| tree | e52e72c8baca7f900d183d8ac2d253fc6a927208 /src/soc/intel/common | |
| parent | e03305358ffa30dbb89adbd0c6c26710c2a1be20 (diff) | |
src/soc/intel/common: Fix CID 1295499, remove dead code
Restructure the nvm_is_write_protected routine to eliminate the dead
code error.
TEST=Build and run on Kunimitsu
Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/nvm.c | 39 |
1 files changed, 20 insertions, 19 deletions
diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index e55638aade..99dcaac39e 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -15,14 +15,13 @@ #include <stdint.h> #include <stddef.h> +#include <bootmode.h> #include <console/console.h> #include <string.h> #include <spi-generic.h> #include <spi_flash.h> #include <soc/spi.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> -#endif #include "nvm.h" /* This module assumes the flash is memory mapped just below 4GiB in the @@ -96,29 +95,31 @@ int nvm_write(void *start, const void *data, size_t size) /* Read flash status register to determine if write protect is active */ int nvm_is_write_protected(void) { - u8 sr1; - u8 wp_gpio = 0; - u8 wp_spi; - if (nvm_init() < 0) return -1; -#if IS_ENABLED(CONFIG_CHROMEOS) - /* Read Write Protect GPIO if available */ - wp_gpio = get_write_protect_state(); -#endif + if (IS_ENABLED(CONFIG_CHROMEOS)) { + u8 sr1; + u8 wp_gpio; + u8 wp_spi; - /* Read Status Register 1 */ - if (flash->status(flash, &sr1) < 0) { - printk(BIOS_ERR, "Failed to read SPI status register 1\n"); - return -1; - } - wp_spi = !!(sr1 & 0x80); + /* Read Write Protect GPIO if available */ + wp_gpio = get_write_protect_state(); + + /* Read Status Register 1 */ + if (flash->status(flash, &sr1) < 0) { + printk(BIOS_ERR, + "Failed to read SPI status register 1\n"); + return -1; + } + wp_spi = !!(sr1 & 0x80); - printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", - wp_gpio, wp_spi); + printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", + wp_gpio, wp_spi); - return wp_gpio && wp_spi; + return wp_gpio && wp_spi; + } + return 0; } /* Apply protection to a range of flash */ |