diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-06-28 15:41:07 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-06-29 23:15:48 +0200 |
| commit | c14a1a940f06546e0135d2c165d1706e2827818e (patch) | |
| tree | 96b6eeae8227f508d560d0b9de75ed80b1acf1c6 /src/soc/intel/common | |
| parent | ed114da4370ebee5126e8faf4eb0f1c9b96b32db (diff) | |
soc/intel/{common,skylake}: provide common NHLT SoC support
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides()
functions should be able to be leveraged on all Intel SoCs
which support NHLT. Therefore provide that functionality and
make skylake use it.
Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/nhlt.c | 41 |
3 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index fdd8f0436e..776004b1d6 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -99,4 +99,8 @@ config SOC_INTEL_COMMON_ACPI bool default n +config SOC_INTEL_COMMON_NHLT + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 88d5fd2c78..e9ad5082b4 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -20,6 +20,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c new file mode 100644 index 0000000000..d498152406 --- /dev/null +++ b/src/soc/intel/common/nhlt.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <nhlt.h> +#include <soc/acpi.h> + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); +} + +uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, + oem_id, oem_table_id); +} |