diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-13 16:55:28 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-21 20:09:31 +0200 |
| commit | bbbfbf2e0fe3c1af135a955505b6a2fd73681a8e (patch) | |
| tree | 529f7c43739edd0b4400c7d9e69c7c6e4aa93569 /src/soc/intel/common | |
| parent | 367ddc91fffafac2c5c78df62bf34305ae11778c (diff) | |
intel fsp: remove CHIPSET_RESERVED_MEM_BYTES
FSP 1.1 platforms should be conforming to the spec. In order
to ensure following specification remove the crutch that allows
FSP to no conform.
BUG=chrome-os-partner:41961
BRANCH=None
TEST=Built.
Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a
Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285187
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 12 | ||||
| -rw-r--r-- | src/soc/intel/common/raminit.c | 5 |
2 files changed, 0 insertions, 17 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 3d0c0eff78..68d3f5ea6c 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -36,18 +36,6 @@ endif # CACHE_MRC_SETTINGS endif # HAVE_MRC -config CHIPSET_RESERVED_MEM_BYTES - hex "Size in bytes of chipset reserved memory area" - default 0 - help - If insufficient documentation is available to determine the size of - the chipset reserved memory area by walking the chipset registers, - the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account - for the missing pieces of memory. The value specified in bytes is: - - value = TSEG base - top of low usable memory - (any sizes determined - by reading chipset registers) - config DISPLAY_MTRRS bool "MTRRs: Display the MTRR settings" default n diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c index 0e764cd18b..69ae1146a4 100644 --- a/src/soc/intel/common/raminit.c +++ b/src/soc/intel/common/raminit.c @@ -153,8 +153,6 @@ void raminit(struct romstage_params *params) #endif /* Migrate CAR data */ - printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", - CONFIG_CHIPSET_RESERVED_MEM_BYTES); printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); if (pei_ptr->boot_mode != SLEEP_STATE_S3) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, @@ -268,9 +266,6 @@ void raminit(struct romstage_params *params) - cbmem_root->PhysicalStart - cbmem_root->ResourceLength; printk(BIOS_DEBUG, - "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", - CONFIG_CHIPSET_RESERVED_MEM_BYTES); - printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); die("Please verify the chipset reserved size\n"); |