soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper

This patch ensures coreboot is not publishing above 4GB mmio resource
if soc common config "enable_above_4GB_mmio" not enable.

Publishing unnecessary 4GB above MMIO resource with wrong base and size
is causing problem while working with discrete GPU.

Unable to boot with dGPU on IA platform with below error:

[    2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[    2.302858] pcieport 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    2.309427] pcieport 0000:00:1c.0:   bridge window [mem 0xb2000000-0xb20fffff]
[    2.316679] pcieport 0000:00:1c.0:   bridge window [mem 0x840000000-0x8c01fffff 64bit pref]
[    2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[    2.330502] pcieport 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    2.337062] pcieport 0000:00:1c.0:   bridge window [mem 0xb2000000-0xb20fffff]
[    2.344317] pcieport 0000:00:1c.0:   bridge window [mem 0xa0000000-0xb01fffff 64bit pref]
[    2.352541] [drm] Not enough PCI address space for a large BAR.

Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>

6 files changed, 56 insertions, 22 deletions

diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index 8e8241bc78..e94c49f7c8 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -47,6 +47,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	U2WE,	16,	// 0x2b - 0x2c USB2 Wake Enable Bitmap
 	U3WE,	16,	// 0x2d - 0x2e USB3 Wake Enable Bitmap
 	UIOR,	8,	// 0x2f - UART debug controller init on S3 resume
+	E4GM,	8,	// 0x30 - Enable above 4GB MMIO Resource
+	A4GB,	64,	// 0x31 - 0x38 Base of above 4GB MMIO Resource
+	A4GS,	64,	// 0x39 - 0x40 Length of above 4GB MMIO Resource
 
 	/* ChromeOS specific */
 	Offset (0x100),
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index 2372e7947b..d271ddac3c 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -16,9 +16,6 @@
 
 #include <soc/iomap.h>
 
-#define BASE_32GB	0x800000000
-#define SIZE_16GB	0x400000000
-
 Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
 Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
 Name (_SEG, Zero)  // _SEG: PCI Segment
@@ -204,20 +201,18 @@ Method (_CRS, 0, Serialized)
 	Add (Subtract (PMAX, PMIN), 1, PLEN)
 
 	/* Patch PM02 range based on Memory Size */
-	CreateQwordField (MCRS, PM02._MIN, MMIN)
-	CreateQwordField (MCRS, PM02._MAX, MMAX)
-	CreateQwordField (MCRS, PM02._LEN, MLEN)
-
-	Store (\_SB.PCI0.MCHC.TUUD, Local0)
-
-	If (LLessEqual (Local0, BASE_32GB)) {
-		Store (BASE_32GB, MMIN)
-		Store (SIZE_16GB, MLEN)
+	If (LEqual (A4GS, 0)) {
+		CreateQwordField (MCRS, PM02._LEN, MSEN)
+		Store (0, MSEN)
 	} Else {
-		Store (0, MMIN)
-		Store (0, MLEN)
+		CreateQwordField (MCRS, PM02._MIN, MMIN)
+		CreateQwordField (MCRS, PM02._MAX, MMAX)
+		CreateQwordField (MCRS, PM02._LEN, MLEN)
+		/* Set 64bit MMIO resource base and length */
+		Store (A4GS, MLEN)
+		Store (A4GB, MMIN)
+		Subtract (Add (MMIN, MLEN), 1, MMAX)
 	}
-	Subtract (Add (MMIN, MLEN), 1, MMAX)
 
 	Return (MCRS)
 }
diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h
index e7e381bfe4..d90714792e 100644
--- a/src/soc/intel/common/block/include/intelblocks/cfg.h
+++ b/src/soc/intel/common/block/include/intelblocks/cfg.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2018-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -37,6 +37,7 @@ struct soc_intel_common_config {
 	/* PCH Thermal Trip Temperature in deg C */
 	uint8_t pch_thermal_trip;
 	struct mmc_dll_params emmc_dll;
+	int enable_above_4GB_mmio;
 };
 
 /* This function to retrieve soc config structure required by common code */
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 5f367b68b3..30502f1ccc 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -38,7 +38,10 @@ typedef struct global_nvs_t {
 	u16	u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
 	u16	u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
 	u8	uior; /* 0x2f - UART debug controller init on S3 resume */
-	u8	unused[208];
+	u8	e4gm; /* 0x30 - Enable above 4GB MMIO Resource */
+	u64	a4gb; /* 0x31 - 0x38 Base of above 4GB MMIO Resource */
+	u64	a4gs; /* 0x39 - 0x40 Length of above 4GB MMIO Resource */
+	u8	unused[191];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t	chromeos;
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 163d97e899..c60595835a 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2017 Intel Corporation.
+ * Copyright 2017-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,6 +18,7 @@
 
 #include <device/device.h>
 #include <soc/iomap.h>
+#include <soc/nvs.h>
 #include <stddef.h>
 
 /* Device 0:0.0 PCI configuration space */
@@ -82,6 +83,8 @@ uintptr_t sa_get_gsm_base(void);
 uintptr_t sa_get_tseg_base(void);
 /* API to get TSEG size */
 size_t sa_get_tseg_size(void);
+/* Fill MMIO resource above 4GB into GNVS */
+void sa_fill_gnvs(global_nvs_t *gnvs);
 /*
  * SoC overrides
  *
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 2da3992ca4..0fab7d9619 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2017-2018 Intel Corporation.
+ * Copyright (C) 2017-2020 Intel Corporation.
  * Copyright (C) 2019 Siemens AG
  *
  * This program is free software; you can redistribute it and/or modify
@@ -14,12 +14,13 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
 #include <cbmem.h>
+#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <intelblocks/acpi.h>
+#include <intelblocks/cfg.h>
 #include <intelblocks/systemagent.h>
 #include <smbios.h>
 #include <soc/iomap.h>
@@ -54,6 +55,34 @@ __weak unsigned long sa_write_acpi_tables(struct device *dev,
 }
 
 /*
+ * This function will get above 4GB mmio enable config specific to soc.
+ *
+ * Return values:
+ *  0 = Above 4GB memory is not enable
+ *  1 = Above 4GB memory is enable
+ */
+static int get_enable_above_4GB_mmio(void)
+{
+	const struct soc_intel_common_config *common_config;
+	common_config = chip_get_common_soc_structure();
+
+	return common_config->enable_above_4GB_mmio;
+}
+
+/* Fill MMIO resource above 4GB into GNVS */
+void sa_fill_gnvs(global_nvs_t *gnvs)
+{
+	if (get_enable_above_4GB_mmio()) {
+		gnvs->e4gm = 1;
+		gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS;
+		gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE;
+		printk(BIOS_DEBUG,
+			"PCI space above 4GB MMIO is from 0x%llx  to len = 0x%llx\n",
+				gnvs->a4gb, gnvs->a4gs);
+	}
+}
+
+/*
  * Add all known fixed MMIO ranges that hang off the host bridge/memory
  * controller device.
  */