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authorChristian Walter <christian.walter@9elements.com>2019-05-28 13:36:07 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-06-03 13:35:39 +0000
commit4b55935173d2267635486d13016c7148f1e2955d (patch)
tree098ef22b12101f173f03fb39e7e32d65d1eaffb3 /src/soc/intel/common
parent920bab553ef51ae33d2a87a1e1ff951149624d2c (diff)
src/soc/intel/common/block/sgx: Add missing new lines
Added missing new lines to Debug Output. Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/sgx/sgx.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 2d4cc53aa7..60714d9ce2 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -100,8 +100,8 @@ void prmrr_core_configure(void)
return;
}
- printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx", prmrr_base.data64);
- printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx", prmrr_mask.data64);
+ printk(BIOS_INFO, "SGX: prmrr_base = 0x%llx\n", prmrr_base.data64);
+ printk(BIOS_INFO, "SGX: prmrr_mask = 0x%llx\n", prmrr_mask.data64);
/* Program core PRMRR MSRs.
* - Set cache writeback mem attrib in PRMRR base MSR