diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-10-05 10:31:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-26 11:20:00 +0000 |
| commit | 0f5d7b9daf3b2c7a2991c62580c9db9c3e8ac953 (patch) | |
| tree | 08f09ecf8980eaf664f24501d54b91df26127ec8 /src/soc/intel/common | |
| parent | c308554c10a33c977657b627c880cde60a590eb4 (diff) | |
soc/intel/cannonlake: Add back PM TIMER EMULATION
ACPI PM timer emulation will be added back as default FSP stops TCO count
for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER
EMULATION will help UEFI payload pass, instead of endless loop wait for
ACPI PM timer counter to increase.
BUG=N/A
TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell.
Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28937
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 63b92013a3..09f0fce1a8 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -36,6 +36,7 @@ #define MSR_EMULATE_PM_TMR 0x121 #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_PM_TMR_EN (1 << 16) +#define EMULATE_DELAY_VALUE 0x13 #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) |