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| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-11-17 12:23:04 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-21 23:43:28 +0100 |
| commit | c6ec8dd1cb2303f7f7a71f0f494a6fc30b93dff4 (patch) | |
| tree | 0fee838b6730bdb4faeaafcb9d6560f898e936d3 /src/soc/intel/common | |
| parent | 5c325491ca2f791c46b2b3ca34f4ad1c750ac6f4 (diff) | |
fsp2_0: implement stage cache for silicon init
Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms
Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common')
0 files changed, 0 insertions, 0 deletions