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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-07-09 13:35:11 -0600
committerMartin Roth <martinroth@google.com>2019-07-11 15:02:18 +0000
commit69d73e4d75f3a133a7307f2daea8773ec7038af5 (patch)
treeb855b7bd14c019ccd3e34b4aefa67ad662315524 /src/soc/intel/common
parent489c722dccbf7b57cab6f1b0e17a14e889d9da4e (diff)
soc/intel/intelblocks/gpio: Always expose GPIO PM constants
These constants are needed in some ASL files, even when __ACPI__ is defined. Change-Id: I0f4f00b93d5d45794b7c9e0f72b51f3191eb3902 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34177 Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index a2cccc7cd2..9b351a938f 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -20,9 +20,6 @@
#include <soc/gpio.h>
#include "gpio_defs.h"
-#ifndef __ACPI__
-#include <types.h>
-
/* GPIO community IOSF sideband clock gating */
#define MISCCFG_GPSIDEDPCGEN (1 << 5)
/* GPIO community RCOMP clock gating */
@@ -40,6 +37,9 @@
MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
| MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+#ifndef __ACPI__
+#include <types.h>
+
/*
* GPIO numbers may not be contiguous and instead will have a different
* starting pin number for each pad group.