aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/common/vbt.h
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2019-04-11 13:07:00 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-04-19 01:40:37 +0000
commit357e5525620021db6e53e225bfa4776dc1b84a91 (patch)
treee46a226e0ad76de6a38f9db9d387ad192bfb3f3e /src/soc/intel/common/vbt.h
parentfc5a3c949dd7ea2aa1d495fb59bbca32e96c0ef6 (diff)
soc/intel/common: Inject SMBIOS type 16 table
Add SMBIOS type 16 table for physical memory array, there's two item had been left over.ECC and max capacity, as of now we set it to fixed value as all the platform support by Intel common code don't support ECC memory and so far the biggest capacity is 32GB. BUG=b:129485635 TEST=Boot up with Sarien platform and check with dmidecode, the following is the result: Handle 0x000D, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 2 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32286 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/vbt.h')
0 files changed, 0 insertions, 0 deletions