Intel Common SOC: Add romstage support

Provide a common romstage implementation for the Intel SOCs.

BRANCH=none
BUG=None
TEST=Build for Braswell

Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 31 insertions, 0 deletions

diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h
new file mode 100644
index 0000000000..db2b0ef455
--- /dev/null
+++ b/src/soc/intel/common/util.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _INTEL_COMMON_UTIL_H_
+#define _INTEL_COMMON_UTIL_H_
+
+#include <arch/cpu.h>
+#include <stdint.h>
+
+asmlinkage void soc_display_mtrrs(void);
+void soc_display_upd_value(const char *name, uint32_t size, uint64_t old,
+	uint64_t new);
+uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
+
+#endif /* _INTEL_COMMON_UTIL_H_ */