diff options
author | Aaron Durbin <adurbin@chromium.org> | 2017-12-14 15:32:37 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-12-16 04:15:29 +0000 |
commit | 2b96f421e6539ceae5c1d0dcd07ed4dfe8a6016a (patch) | |
tree | 1a22758a7efb32f14193cadedacb339ab013bece /src/soc/intel/common/spi_flash.h | |
parent | 410f3b402a29af09070520bd13ea90e75ae2f5ec (diff) |
soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region()
In the fast spi support implement the callback for flash_protect().
This removes the need for having SOC_INTEL_COMMON_SPI_FLASH_PROTECT
Kconfig option as well spi_flash_get_fpr_info() and separate
spi_flash.[ch].
BUG=b:69614064
Change-Id: Iaf3b599a13a756262d3f36bae60de4f7fd00e7dc
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/common/spi_flash.h')
-rw-r--r-- | src/soc/intel/common/spi_flash.h | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/src/soc/intel/common/spi_flash.h b/src/soc/intel/common/spi_flash.h deleted file mode 100644 index d6bb079dbb..0000000000 --- a/src/soc/intel/common/spi_flash.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __INTEL_COMMON_SPI_FLASH_H__ -#define __INTEL_COMMON_SPI_FLASH_H__ - -#define SPI_FPR_SHIFT 12 -#define SPI_FPR_MASK 0x7fff -#define SPI_FPR_BASE_SHIFT 0 -#define SPI_FPR_LIMIT_SHIFT 16 -#define SPI_FPR_RPE (1 << 15) /* Read Protect */ -#define SPI_FPR_WPE (1 << 31) /* Write Protect */ -#define SPI_FPR(base, limit) \ - (((((limit) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_LIMIT_SHIFT) |\ - ((((base) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT)) - -struct fpr_info { - /* Offset of first FPR register */ - uintptr_t base; - /* Maximum number of FPR registers */ - uint8_t max; -}; - -/* - * SoC is expected to implement this function to provide address of first FPR - * register and max count of FPR registers. - * - * On success return 0 else -1. - */ -int spi_flash_get_fpr_info(struct fpr_info *info); - -/* - * Protect range of SPI flash defined by [start, start+size-1] using Flash - * Protected Range (FPR) register if available. - */ -int spi_flash_protect(u32 start, u32 size); - -#endif /* __INTEL_COMMON_SPI_FLASH_H__ */ |