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| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-13 13:50:34 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-21 20:07:03 +0200 |
| commit | 27d153cabc899ab94ea28d3c7ce5ca56ecefb7ce (patch) | |
| tree | e28a0efcff92dad66ed238afe75e3b6744939a2d /src/soc/intel/common/reset.c | |
| parent | f077de66ffdbbd191f09ae8a4d6f08d0313be90f (diff) | |
skylake: re-enable PCIe L1 sub states
All boards should have their L1 sub states working now so
re-enable the defaults.
BUG=chrome-os-partner:41861
BRANCH=None
TEST=Built and booted glados into OS. PCIe devices show up still.
Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36
Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285170
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10989
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/reset.c')
0 files changed, 0 insertions, 0 deletions