Revert "soc/intel: Refactor do_global_reset() function"

This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719.

Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541

Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

1 files changed, 1 insertions, 20 deletions

diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index ca31897c12..c6c394bd44 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -4,35 +4,16 @@
 #include <cf9_reset.h>
 #include <console/console.h>
 #include <halt.h>
-#include <intelblocks/cse.h>
-#include <intelblocks/pmclib.h>
 #include <reset.h>
 
 #include "reset.h"
 
-static void force_global_reset(void)
-{
-	/* Ask CSE to do the global reset */
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_CSE))
-		if (cse_request_global_reset())
-			return;
-
-	/*
-	 * If ME is unable to reset platform then enable the PMC CF9GR register [B0:D31:F2
-	 * register offset 0xAC bit 20] and force a global reset by writing 0x06 or 0x0E.
-	 */
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_PMC))
-		pmc_global_reset_enable(true);
-	/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port to global reset platform */
-	do_full_reset();
-}
-
 void global_reset(void)
 {
 	printk(BIOS_INFO, "%s() called!\n", __func__);
 	cf9_reset_prepare();
 	dcache_clean_all();
-	force_global_reset();
+	do_global_reset();
 	halt();
 }