diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-10-15 12:07:03 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-27 15:19:03 +0100 |
commit | 94b856ef9afaca880909d22b24d5443408c47920 (patch) | |
tree | 14a76715a13535b5c2991103adf4820f776f1dd5 /src/soc/intel/common/ramstage.h | |
parent | 597de2849d8a0861ba0d7fca32948bdf37378eed (diff) |
FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values
associated with this common code.
BRANCH=none
BUG=None
TEST=Build and run on kunimitsu
Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/common/ramstage.h')
-rw-r--r-- | src/soc/intel/common/ramstage.h | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h deleted file mode 100644 index d6cb895174..0000000000 --- a/src/soc/intel/common/ramstage.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _INTEL_COMMON_RAMSTAGE_H_ -#define _INTEL_COMMON_RAMSTAGE_H_ - -#include <fsp/util.h> -#include <soc/intel/common/util.h> -#include <stdint.h> - -/* Perform Intel silicon init. */ -void intel_silicon_init(void); -/* Called after the silicon init code has run. */ -void soc_after_silicon_init(void); -/* Initialize UPD data before SiliconInit call. */ -void soc_silicon_init_params(SILICON_INIT_UPD *params); -void mainboard_silicon_init_params(SILICON_INIT_UPD *params); -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new); -void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); - -#endif /* _INTEL_COMMON_RAMSTAGE_H_ */ |