diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-16 15:18:04 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:54:53 +0000 |
| commit | e1ecfc93af4918c2a9a4647cf550cb7ecc2b92d6 (patch) | |
| tree | f86a6b4fdec14666a4e0fca1618441f52ea526ad /src/soc/intel/common/raminit.c | |
| parent | 8ef9c5660211719f974da1c452257a94c167bfed (diff) | |
intel: update common and FSP cache-as-ram parameters
Instead of just passing bits, tsc_low, tsc_high, and an
opaque pointer to chipset context those fields are bundled
into a cache_as_ram_params struct. Additionally, a new
struct fsp_car_context is created to hold the FSP
information. These could be combined as the existing
romstage code assumes what the chipset_context values are, but
I'm leaving the concept of "common" alone for the time being.
While working in that area the ABI between assembly and C code
has changed to just pass a single pointer to cache_as_ram_params
struct. Lastly, validate the bootloader cache-as-ram region
with the Kconfig options.
BUG=chrome-os-partner:44676
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/300190
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/common/raminit.c')
| -rw-r--r-- | src/soc/intel/common/raminit.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c index bdb23e2b64..932d5c36e8 100644 --- a/src/soc/intel/common/raminit.c +++ b/src/soc/intel/common/raminit.c @@ -57,6 +57,7 @@ void raminit(struct romstage_params *params) unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; #endif + struct fsp_car_context *fsp_car_context; /* * Find and copy the UPD region to the stack so the platform can modify @@ -68,7 +69,8 @@ void raminit(struct romstage_params *params) * region in the FSP binary. */ post_code(0x34); - fsp_header = params->chipset_context; + fsp_car_context = params->chipset_context; + fsp_header = fsp_car_context->fih; vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + fsp_header->ImageBase); printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); @@ -167,7 +169,7 @@ void raminit(struct romstage_params *params) } /* Save the FSP runtime parameters. */ - fsp_set_runtime(params->chipset_context, hob_list_ptr); + fsp_set_runtime(fsp_header, hob_list_ptr); /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); |