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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-23 21:21:51 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-29 21:51:50 +0000
commit81bcce9c8d526cd772e26579c1458b00e53713d2 (patch)
tree54e5cbcebc9534975f0e19852706f846a0e5be3a /src/soc/intel/common/nhlt.c
parentc657ab9750dd040db2af9011d32c112bcdca8a5d (diff)
soc/intel/common/irq: Add function to program north PCI IRQs
Because the FSP interface for PCI IRQs only includes the PCH devices, this function is the complement to that, taking the list of irq entries, and programming the PCI_INTERRUPT_LINE registers. BUG=b:130217151, b:171580862, b:176858827 TEST=boot brya with patch train, verify with `lspci -vvv` that for all the north PCI devices, their IRQ was either the one programmed by this function, or an MSI was used. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I81cf7b25f115e41deb25767669b5466b5712b177 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55817 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/nhlt.c')
0 files changed, 0 insertions, 0 deletions