soc/intel/cnvi: Add power related methods

Only the _PRR method is used here, however, _PS0, _PS3 and _DSW must
exist to avoid a BSOD on Windows.

Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>

1 files changed, 22 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index fcfb03fd1b..eff5044907 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -316,6 +316,28 @@ static void cnvw_fill_ssdt(const struct device *dev)
 	}
 	acpigen_pop_len();
 
+/*
+ *	Method (_PS0, 0, Serialized)
+ *	{
+ *	}
+ *
+ *	Method (_PS3, 0, Serialized)
+ *	{
+ *	}
+ *
+ *	Method (_DSW, 3)
+ *	{
+ *	}
+ */
+	acpigen_write_method_serialized("_PS0", 0);
+	acpigen_pop_len();
+
+	acpigen_write_method_serialized("_PS3", 0);
+	acpigen_pop_len();
+
+	acpigen_write_method("_DSW", 3);
+	acpigen_pop_len();
+
 	acpigen_write_scope_end();
 }