soc/intel/cmd/blk/cse: Implement APIs to access CMOS CSE FPT versions

This patch implements APIs to access the CSE FW partition versions in
CMOS. The get API allows users to retrieve the current version from
CMOS memory. The set API allows users to set the version in CMOS
memory.

BUG=b:280722061
TEST=APIs verified on rex board.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

4 files changed, 77 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index b6e2ecb6d4..1acad624b6 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -62,6 +62,15 @@ config SOC_INTEL_STORE_CSE_FW_VERSION
 	  ensure this feature is platform specific and only enabled for the platform
 	  that would like to store the CSE version into the CBMEM.
 
+config SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET
+	int
+	default 68
+	depends on SOC_INTEL_CSE_LITE_SKU
+	help
+	  This configuration option stores the starting offset of cse fw partition versions in
+	  CMOS memory. The offset should be byte aligned and must leave enough memory to store
+	  required firmware partition versions.
+
 config SOC_INTEL_STORE_ISH_FW_VERSION
 	bool
 	default n
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc
index ad15dc4f94..6798c684e5 100644
--- a/src/soc/intel/common/block/cse/Makefile.inc
+++ b/src/soc/intel/common/block/cse/Makefile.inc
@@ -3,6 +3,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
 romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
 ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c
+ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite_cmos.c
+romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite_cmos.c
 ramstage-$(CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT) += cse_spec.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
 smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
diff --git a/src/soc/intel/common/block/cse/cse_lite_cmos.c b/src/soc/intel/common/block/cse/cse_lite_cmos.c
new file mode 100644
index 0000000000..5fc3fb0e42
--- /dev/null
+++ b/src/soc/intel/common/block/cse/cse_lite_cmos.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <ip_checksum.h>
+#include <pc80/mc146818rtc.h>
+
+#include "cse_lite_cmos.h"
+
+/*
+ * We need a region in CMOS to store the firmware versions.
+ *
+ * This can either be declared as part of the option
+ * table or statically defined in the board config.
+ */
+#if CONFIG(USE_OPTION_TABLE)
+# include "option_table.h"
+
+#ifndef CMOS_VSTART_partition_fw
+#error "The `ramtop` CMOS entry is missing, please add it to your cmos.layout."
+#endif
+
+#if CMOS_VSTART_partition_fw % 8 != 0
+#error "The `partition firmware` CMOS entry needs to be byte aligned, check your cmos.layout."
+#endif	// CMOS_VSTART_partition_fw % 8 != 0
+
+#if CMOS_VLEN_partition_fw != (32 * 8)
+#error "The partition firmware entry needs to be 32 bytes long, check your cmos.layout."
+#endif
+
+# define PARTITION_FW_CMOS_OFFSET (CMOS_VSTART_partition_fw >> 3)
+
+#else
+# if (CONFIG_SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET != 0)
+#  define PARTITION_FW_CMOS_OFFSET CONFIG_SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET
+# else
+#  error "Must configure CONFIG_SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET"
+# endif
+#endif
+
+/* Helper function to read CSE fpt information from cmos memory. */
+void cmos_read_fw_partition_info(struct cse_specific_info *info)
+{
+	for (uint8_t *p = (uint8_t *)info, i = 0; i < sizeof(*info); i++, p++)
+		*p = cmos_read(PARTITION_FW_CMOS_OFFSET + i);
+}
+
+/* Helper function to write CSE fpt information to cmos memory. */
+void cmos_write_fw_partition_info(const struct cse_specific_info *info)
+{
+	for (uint8_t *p = (uint8_t *)info, i = 0; i < sizeof(*info); i++, p++)
+		cmos_write(*p, PARTITION_FW_CMOS_OFFSET + i);
+}
diff --git a/src/soc/intel/common/block/cse/cse_lite_cmos.h b/src/soc/intel/common/block/cse/cse_lite_cmos.h
new file mode 100644
index 0000000000..a6dd6ce7f2
--- /dev/null
+++ b/src/soc/intel/common/block/cse/cse_lite_cmos.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_CSE_LITE_CMOS_H
+#define SOC_INTEL_COMMON_BLOCK_CSE_LITE_CMOS_H
+
+#include <intelblocks/cse.h>
+
+/* Helper function to read CSE fpt information from cmos memory. */
+void cmos_read_fw_partition_info(struct cse_specific_info *info);
+
+/* Helper function to write CSE fpt information to cmos memory. */
+void cmos_write_fw_partition_info(const struct cse_specific_info *info);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_CSE_LITE_CMOS_H */