soc/intel/common/block: Add Intel common FAST_SPI code

Create Intel Common FAST_SPI Controller code.

This code contains the code for SPI initialization which has
the following programming -

* Get BIOS Rom Region Size
* Enable SPIBAR
* Disable the BIOS write protect so write commands are allowed
* Enable SPI Prefetching and Caching.
* SPI Controller register offsets in the common header fast_spi.h
* Implement FAST_SPI read, write, erase APIs.

Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

6 files changed, 806 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig
new file mode 100644
index 0000000000..87edb92095
--- /dev/null
+++ b/src/soc/intel/common/block/fast_spi/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_FAST_SPI
+	bool
+	help
+	  Intel Processor common FAST_SPI support
diff --git a/src/soc/intel/common/block/fast_spi/Makefile.inc b/src/soc/intel/common/block/fast_spi/Makefile.inc
new file mode 100644
index 0000000000..9c75f3bc46
--- /dev/null
+++ b/src/soc/intel/common/block/fast_spi/Makefile.inc
@@ -0,0 +1,21 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
+
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
+
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
+
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
+
+ifeq ($(CONFIG_SPI_FLASH_SMM),y)
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI) += fast_spi_flash.c
+endif
+
+CPPFLAGS_common += -I$(src)/soc/intel/common/block/fast_spi
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
new file mode 100644
index 0000000000..603af16881
--- /dev/null
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -0,0 +1,205 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <assert.h>
+#include <device/pci_def.h>
+#include <commonlib/helpers.h>
+#include <console/console.h>
+#include <fast_spi_def.h>
+#include <intelblocks/fast_spi.h>
+#include <soc/intel/common/spi_flash.h>
+#include <soc/pci_devs.h>
+#include <spi_flash.h>
+#include <spi-generic.h>
+#include <stdlib.h>
+#include <string.h>
+
+/*
+ * Get the FAST_SPIBAR.
+ */
+void *fast_spi_get_bar(void)
+{
+	device_t dev = PCH_DEV_SPI;
+	uintptr_t bar;
+
+	bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	assert(bar != 0);
+	/*
+	 * Bits 31-12 are the base address as per EDS for SPI,
+	 * Don't care about 0-11 bit
+	 */
+	return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
+}
+
+/*
+ * Disable the BIOS write protect and Enable Prefetching and Caching.
+ */
+void fast_spi_init(void)
+{
+	device_t dev = PCH_DEV_SPI;
+	uint8_t bios_cntl;
+
+	bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
+
+	/* Disable the BIOS write protect so write commands are allowed. */
+	bios_cntl &= ~SPIBAR_BIOS_CONTROL_EISS;
+	bios_cntl |= SPIBAR_BIOS_CONTROL_WPD;
+	/* Enable Prefetching and caching. */
+	bios_cntl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
+	bios_cntl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
+
+	pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
+}
+
+/*
+ * Set FAST_SPIBAR BIOS Control BILD bit.
+ */
+static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit)
+{
+	device_t dev = PCH_DEV_SPI;
+	uint8_t bc_cntl;
+
+	assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
+	bc_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
+	bc_cntl |= bios_cntl_bit;
+	pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_cntl);
+}
+
+/*
+ * Set FAST_SPIBAR BIOS Control BILD bit.
+ */
+void fast_spi_set_bios_interface_lock_down(void)
+{
+	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_BILD);
+}
+
+/*
+ * Set FAST_SPIBAR BIOS Control LE bit.
+ */
+void fast_spi_set_lock_enable(void)
+{
+	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE);
+}
+
+/*
+ * Set FAST_SPIBAR BIOS Control EISS bit.
+ */
+void fast_spi_set_eiss(void)
+{
+	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EISS);
+}
+
+/*
+ * Set FAST_SPI opcode menu.
+ */
+void fast_spi_set_opcode_menu(void)
+{
+	void *spibar = fast_spi_get_bar();
+
+	write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX);
+	write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE);
+	write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER);
+	write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER);
+}
+
+/*
+ * Lock FAST_SPIBAR.
+ */
+void fast_spi_lock_bar(void)
+{
+	void *spibar = fast_spi_get_bar();
+	uint32_t hsfs;
+
+	hsfs = read32(spibar + SPIBAR_HSFSTS_CTL);
+	hsfs |= SPIBAR_HSFSTS_FLOCKDN;
+	write32(spibar + SPIBAR_HSFSTS_CTL, hsfs);
+}
+
+/*
+ * Set FAST_SPIBAR Soft Reset Data Register value.
+ */
+void fast_spi_set_strap_msg_data(uint32_t soft_reset_data)
+{
+	void *spibar = fast_spi_get_bar();
+	uint32_t ssl, ssms;
+
+	/* Set Strap Lock Disable */
+	ssl = read32(spibar + SPIBAR_RESET_LOCK);
+	ssl &= ~SPIBAR_RESET_LOCK_ENABLE;
+	write32(spibar + SPIBAR_RESET_LOCK, ssl);
+
+	/* Write Soft Reset Data register at SPIBAR0 offset 0xF8[0:15] */
+	write32(spibar + SPIBAR_RESET_DATA, soft_reset_data);
+
+	/* Set Strap Mux Select  set to '1' */
+	ssms = read32(spibar + SPIBAR_RESET_CTRL);
+	ssms |= SPIBAR_RESET_CTRL_SSMC;
+	write32(spibar + SPIBAR_RESET_CTRL, ssms);
+
+	/* Set Strap Lock Enable */
+	ssl = read32(spibar + SPIBAR_RESET_LOCK);
+	ssl |= SPIBAR_RESET_LOCK_ENABLE;
+	write32(spibar + SPIBAR_RESET_LOCK, ssl);
+}
+
+/*
+ * Returns bios_start and fills in size of the BIOS region.
+ */
+size_t fast_spi_get_bios_region(size_t *bios_size)
+{
+	size_t bios_start, bios_end;
+	/*
+	 * BIOS_BFPREG provides info about BIOS Flash Primary Region
+	 * Base and Limit.
+	 * Base and Limit fields are in units of 4KiB.
+	 */
+	uint32_t val = read32(fast_spi_get_bar() + SPIBAR_BFPREG);
+
+	bios_start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
+	bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
+		     SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB;
+	*bios_size = bios_end - bios_start;
+	return bios_start;
+}
+
+/*
+ * Program temporary BAR for SPI in case any of the stages before ramstage need
+ * to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI
+ * enumeration.
+ */
+void fast_spi_early_init(uintptr_t spi_base_address)
+{
+	device_t dev = PCH_DEV_SPI;
+	uint8_t pcireg;
+
+	/* Assign Resources to SPI Controller */
+	/* Clear BIT 1-2 SPI Command Register */
+	pcireg = pci_read_config8(dev, PCI_COMMAND);
+	pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+	pci_write_config8(dev, PCI_COMMAND, pcireg);
+
+	/* Program Temporary BAR for SPI */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0,
+		spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
+
+	/* Enable Bus Master and MMIO Space */
+	pcireg = pci_read_config8(dev, PCI_COMMAND);
+	pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config8(dev, PCI_COMMAND, pcireg);
+
+	/* Initialize SPI to allow BIOS to write/erase on flash. */
+	fast_spi_init();
+}
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
new file mode 100644
index 0000000000..1262e6aed0
--- /dev/null
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H
+#define SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H
+
+/* PCI configuration registers */
+
+#define SPIDVID_OFFSET			0x0
+#define SPIBAR_BIOS_CONTROL		0xdc
+
+/* Bit definitions for BIOS_CONTROL */
+#define SPIBAR_BIOS_CONTROL_WPD 	(1 << 0)
+#define SPIBAR_BIOS_CONTROL_LOCK_ENABLE	(1 << 1)
+#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE	(1 << 2)
+#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE	(1 << 3)
+#define SPIBAR_BIOS_CONTROL_EISS	(1 << 5)
+#define SPIBAR_BIOS_CONTROL_BILD	(1 << 7)
+
+/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
+
+#define SPIBAR_BFPREG			0x00
+#define SPIBAR_HSFSTS_CTL		0x04
+#define SPIBAR_FADDR			0x08
+#define SPIBAR_FDATA(n)			(0x10 + ((n) & 0xf) * 4)
+#define SPIBAR_FPR_BASE			0x84
+#define SPIBAR_FPR(n)			0x84 + (4 * n))
+#define SPIBAR_PREOP			0xA4
+#define SPIBAR_OPTYPE			0xA6
+#define SPIBAR_OPMENU_LOWER		0xA8
+#define SPIBAR_OPMENU_UPPER		0xAc
+#define SPIBAR_FDOC			0xB4
+#define SPIBAR_FDOD			0xB8
+#define SPIBAR_PTINX			0xcc
+#define SPIBAR_PTDATA			0xd0
+
+/* Bit definitions for BFPREG (0x00) register */
+#define SPIBAR_BFPREG_PRB_MASK		(0x7fff)
+#define SPIBAR_BFPREG_PRL_SHIFT	(16)
+#define SPIBAR_BFPREG_PRL_MASK		(0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
+#define SPIBAR_BFPREG_SBRS		(1 << 31)
+
+/* Bit definitions for HSFSTS_CTL (0x04) register */
+#define SPIBAR_HSFSTS_FDBC_MASK	(0x3f << 24)
+#define SPIBAR_HSFSTS_FDBC(n)		(((n) << 24) & SPIBAR_HSFSTS_FDBC_MASK)
+#define SPIBAR_HSFSTS_WET		(1 << 21)
+#define SPIBAR_HSFSTS_FCYCLE_MASK	(0xf << 17)
+#define SPIBAR_HSFSTS_FCYCLE(cyc)	(((cyc) << 17) \
+					& SPIBAR_HSFSTS_FCYCLE_MASK)
+/* Supported flash cycle types */
+#define SPIBAR_HSFSTS_CYCLE_READ	SPIBAR_HSFSTS_FCYCLE(0)
+#define SPIBAR_HSFSTS_CYCLE_WRITE	SPIBAR_HSFSTS_FCYCLE(2)
+#define SPIBAR_HSFSTS_CYCLE_4K_ERASE	SPIBAR_HSFSTS_FCYCLE(3)
+#define SPIBAR_HSFSTS_CYCLE_64K_ERASE	SPIBAR_HSFSTS_FCYCLE(4)
+#define SPIBAR_HSFSTS_CYCLE_RD_STATUS	SPIBAR_HSFSTS_FCYCLE(8)
+
+#define SPIBAR_HSFSTS_FGO		(1 << 16)
+#define SPIBAR_HSFSTS_FLOCKDN		(1 << 15)
+#define SPIBAR_HSFSTS_FDV		(1 << 14)
+#define SPIBAR_HSFSTS_FDOPSS		(1 << 13)
+#define SPIBAR_HSFSTS_SAF_CE		(1 << 8)
+#define SPIBAR_HSFSTS_SAF_ACTIVE	(1 << 7)
+#define SPIBAR_HSFSTS_SAF_LE		(1 << 6)
+#define SPIBAR_HSFSTS_SCIP		(1 << 5)
+#define SPIBAR_HSFSTS_SAF_DLE		(1 << 4)
+#define SPIBAR_HSFSTS_SAF_ERROR		(1 << 3)
+#define SPIBAR_HSFSTS_AEL		(1 << 2)
+#define SPIBAR_HSFSTS_FCERR		(1 << 1)
+#define SPIBAR_HSFSTS_FDONE		(1 << 0)
+#define SPIBAR_HSFSTS_W1C_BITS		(0xff)
+
+#define WPSR_MASK_SRP0_BIT 0x80
+
+/* Bit definitions for FADDR (0x08) register */
+#define SPIBAR_FADDR_MASK		0x7FFFFFF
+
+/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
+#define SPIBAR_FDATA_FIFO_SIZE		0x40
+
+/* Bit definitions for FDOC (0xB4) register */
+#define SPIBAR_FDOC_COMPONENT		(1 << 12)
+#define SPIBAR_FDOC_FDSI_1		(1 << 2)
+
+/* Flash Descriptor Component Section - Component 0 Density Bit Settings */
+#define FLCOMP_C0DEN_MASK		0xF
+#define FLCOMP_C0DEN_8MB		4
+#define FLCOMP_C0DEN_16MB		5
+#define FLCOMP_C0DEN_32MB		6
+
+/* Bit definitions for FPRn (0x84 + (4 * n)) registers */
+#define SPIBAR_FPR_WPE			(1 << 31) /* Flash Write protected */
+#define SPIBAR_FPR_MAX			5
+
+/* Programmable values for OPMENU_LOWER(0xA8) & OPMENU_UPPER(0xAC) register */
+#define SPI_OPMENU_0 			0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 			0x01 /* Write, no address */
+#define SPI_OPMENU_1 			0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 			0x03 /* Write, address required */
+#define SPI_OPMENU_2 			0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 			0x02 /* Read, address required */
+#define SPI_OPMENU_3 			0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 			0x00 /* Read, no address */
+#define SPI_OPMENU_4 			0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 			0x03 /* Write, address required */
+#define SPI_OPMENU_5 			0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 			0x00 /* Read, no address */
+#define SPI_OPMENU_6 			0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 			0x03 /* Write, address required */
+#define SPI_OPMENU_7 			0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7			0x02 /* Read, address required */
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8)  | \
+		    (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4)   | \
+		    (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+
+/* Bit definitions for PTINX (0xCC) register */
+#define SPIBAR_PTINX_COMP_0		(0 << 14)
+#define SPIBAR_PTINX_COMP_1		(1 << 14)
+#define SPIBAR_PTINX_HORD_SFDP		(0 << 12)
+#define SPIBAR_PTINX_HORD_PARAM		(1 << 12)
+#define SPIBAR_PTINX_HORD_JEDEC		(2 << 12)
+#define SPIBAR_PTINX_IDX_MASK		0xffc
+
+/* Register Offsets of BIOS Flash Program Registers */
+#define SPIBAR_RESET_LOCK               0xF0
+#define SPIBAR_RESET_CTRL               0xF4
+#define SPIBAR_RESET_DATA               0xF8
+
+/* Programmable values of Bit0 (SSL) of Set STRAP MSG LOCK (0xF0) Register */
+#define SPIBAR_RESET_LOCK_DISABLE	0 /* Set_Strap Lock(SSL) Bit 0 = 0 */
+#define SPIBAR_RESET_LOCK_ENABLE	1 /* Set_Strap Lock(SSL) Bit 0 = 1 */
+
+/* Programmable values of Bit0(SSMS) of Set STRAP MSG Control (0xF4) Register*/
+#define SPIBAR_RESET_CTRL_SSMC		1 /* Set_Strap Mux Select(SSMS) Bit=1*/
+
+#define SPIBAR_HWSEQ_XFER_TIMEOUT	15 /* 15ms*/
+
+void *fast_spi_get_bar(void);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_FAST_SPI_DEF_H */
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
new file mode 100644
index 0000000000..3babf914b7
--- /dev/null
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
@@ -0,0 +1,352 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <fast_spi_def.h>
+#include <intelblocks/fast_spi.h>
+#include <soc/intel/common/spi_flash.h>
+#include <soc/pci_devs.h>
+#include <spi_flash.h>
+#include <string.h>
+#include <timer.h>
+
+/* Helper to create a FAST_SPI context on API entry. */
+#define BOILERPLATE_CREATE_CTX(ctx)		\
+	struct fast_spi_flash_ctx	real_ctx;	\
+	struct fast_spi_flash_ctx *ctx = &real_ctx;	\
+	_fast_spi_flash_get_ctx(ctx)
+
+/*
+ * Anything that's not success is <0. Provided solely for readability, as these
+ * constants are not used outside this file.
+ */
+enum errors {
+	SUCCESS			= 0,
+	E_TIMEOUT		= -1,
+	E_HW_ERROR		= -2,
+	E_ARGUMENT		= -3,
+};
+
+/* Reduce data-passing burden by grouping transaction data in a context. */
+struct fast_spi_flash_ctx {
+	uintptr_t mmio_base;
+};
+
+static void _fast_spi_flash_get_ctx(struct fast_spi_flash_ctx *ctx)
+{
+	ctx->mmio_base = (uintptr_t)fast_spi_get_bar();
+}
+
+/* Read register from the FAST_SPI flash controller. */
+static uint32_t fast_spi_flash_ctrlr_reg_read(struct fast_spi_flash_ctx *ctx,
+	uint16_t reg)
+{
+	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, sizeof(uint32_t));
+	return read32((void *)addr);
+}
+
+/* Write to register in FAST_SPI flash controller. */
+static void fast_spi_flash_ctrlr_reg_write(struct fast_spi_flash_ctx *ctx,
+					uint16_t reg, uint32_t val)
+{
+	uintptr_t addr =  ALIGN_DOWN(ctx->mmio_base + reg, sizeof(uint32_t));
+	write32((void *)addr, val);
+}
+
+/*
+ * The hardware datasheet is not clear on what HORD values actually do. It
+ * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which
+ * is the signature and revision fields. HORD_JEDEC provides access to the
+ * actual flash parameters, and is most likely what you want to use when
+ * probing the flash from software.
+ * It's okay to rely on SFDP, since the SPI flash controller requires an SFDP
+ * 1.5 or newer compliant FAST_SPI flash chip.
+ * NOTE: Due to the register layout of the hardware, all accesses will be
+ * aligned to a 4 byte boundary.
+ */
+static uint32_t fast_spi_flash_read_sfdp_param(struct fast_spi_flash_ctx *ctx,
+					  uint16_t sfdp_reg)
+{
+	uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK;
+	fast_spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX,
+				   ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
+	return fast_spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA);
+}
+
+/* Fill FDATAn FIFO in preparation for a write transaction. */
+static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const void *data,
+			   size_t len)
+{
+	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
+	memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
+}
+
+/* Drain FDATAn FIFO after a read transaction populates data. */
+static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *dest,
+				size_t len)
+{
+	/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
+	memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
+}
+
+/* Fire up a transfer using the hardware sequencer. */
+static void start_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
+		uint32_t hsfsts_cycle, uint32_t flash_addr, size_t len)
+{
+	/* Make sure all W1C status bits get cleared. */
+	uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS;
+	/* Set up transaction parameters. */
+	hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK;
+	hsfsts |= SPIBAR_HSFSTS_FDBC(len - 1);
+
+	fast_spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr);
+	fast_spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL,
+			     hsfsts | SPIBAR_HSFSTS_FGO);
+}
+
+static int wait_for_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
+					uint32_t flash_addr)
+{
+	struct stopwatch sw;
+	uint32_t hsfsts;
+
+	stopwatch_init_msecs_expire(&sw, SPIBAR_HWSEQ_XFER_TIMEOUT);
+	do {
+		hsfsts = fast_spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
+
+		if (hsfsts & SPIBAR_HSFSTS_FCERR) {
+			printk(BIOS_ERR, "SPI Transaction Error at Flash Offset %x HSFSTS = 0x%08x\n",
+				flash_addr, hsfsts);
+			return E_HW_ERROR;
+		}
+
+		if (hsfsts & SPIBAR_HSFSTS_FDONE)
+			return SUCCESS;
+	} while (!(stopwatch_expired(&sw)));
+
+	printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) at Flash Offset %x HSFSTS = 0x%08x\n",
+		SPIBAR_HWSEQ_XFER_TIMEOUT, flash_addr, hsfsts);
+	return E_TIMEOUT;
+}
+
+/* Execute FAST_SPI flash transfer. This is a blocking call. */
+static int exec_sync_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
+				uint32_t hsfsts_cycle, uint32_t flash_addr,
+				size_t len)
+{
+	start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len);
+	return wait_for_hwseq_xfer(ctx, flash_addr);
+}
+
+/*
+ * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
+ * that the operation does not cross 256-byte boundary.
+ */
+static size_t get_xfer_len(uint32_t addr, size_t len)
+{
+	size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
+	size_t bytes_left = ALIGN_UP(addr, 256) - addr;
+
+	if (bytes_left)
+		xfer_len = min(xfer_len, bytes_left);
+
+	return xfer_len;
+}
+
+
+/* Flash device operations. */
+static struct spi_flash boot_flash CAR_GLOBAL;
+
+static int fast_spi_flash_erase(const struct spi_flash *flash,
+				uint32_t offset, size_t len)
+{
+	int ret;
+	size_t erase_size;
+	uint32_t erase_cycle;
+
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) {
+		printk(BIOS_ERR, "BUG! SPI erase region not sector aligned\n");
+		return E_ARGUMENT;
+	}
+
+	while (len) {
+		if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) {
+			erase_size = 64 * KiB;
+			erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE;
+		} else {
+			erase_size = 4 * KiB;
+			erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE;
+		}
+		printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n",
+		       offset, erase_size / KiB);
+
+		ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0);
+		if (ret != SUCCESS)
+			return ret;
+
+		offset += erase_size;
+		len -= erase_size;
+	}
+
+	return SUCCESS;
+}
+
+static int fast_spi_flash_read(const struct spi_flash *flash,
+			uint32_t addr, size_t len, void *buf)
+{
+	int ret;
+	size_t xfer_len;
+	uint8_t *data = buf;
+
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	while (len) {
+		xfer_len = get_xfer_len(addr, len);
+
+		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ,
+						addr, xfer_len);
+		if (ret != SUCCESS)
+			return ret;
+
+		drain_xfer_fifo(ctx, data, xfer_len);
+
+		addr += xfer_len;
+		data += xfer_len;
+		len -= xfer_len;
+	}
+
+	return SUCCESS;
+}
+
+static int fast_spi_flash_write(const struct spi_flash *flash,
+		uint32_t addr, size_t len, const void *buf)
+{
+	int ret;
+	size_t xfer_len;
+	const uint8_t *data = buf;
+
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	while (len) {
+		xfer_len = get_xfer_len(addr, len);
+		fill_xfer_fifo(ctx, data, xfer_len);
+
+		ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE,
+						addr, xfer_len);
+		if (ret != SUCCESS)
+			return ret;
+
+		addr += xfer_len;
+		data += xfer_len;
+		len -= xfer_len;
+	}
+
+	return SUCCESS;
+}
+
+static int fast_spi_flash_status(const struct spi_flash *flash,
+						uint8_t *reg)
+{
+	int ret;
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
+				   sizeof(*reg));
+	if (ret != SUCCESS)
+		return ret;
+
+	drain_xfer_fifo(ctx, reg, sizeof(*reg));
+	return ret;
+}
+
+/*
+ * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did.
+ * For details see:
+ * Ch 31, SPI: p. 194
+ * The size of the flash component is always taken from density field in the
+ * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller.
+ */
+struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+	struct spi_flash *flash;
+	uint32_t flash_bits;
+
+	flash = car_get_var_ptr(&boot_flash);
+
+	/*
+	 * bytes = (bits + 1) / 8;
+	 * But we need to do the addition in a way which doesn't overflow for
+	 * 4 Gbit devices (flash_bits == 0xffffffff).
+	 */
+	flash_bits = fast_spi_flash_read_sfdp_param(ctx, 0x04);
+	flash->size = (flash_bits >> 3) + 1;
+
+	memcpy(&flash->spi, dev, sizeof(*dev));
+	flash->name = "FAST_SPI Hardware Sequencer";
+
+	/* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */
+	flash->sector_size = 4 * KiB;
+	/*
+	 * FIXME: Get erase+cmd, and status_cmd from SFDP.
+	 *
+	 * flash->erase_cmd = ???
+	 * flash->status_cmd = ???
+	 */
+
+	flash->internal_write = fast_spi_flash_write;
+	flash->internal_erase = fast_spi_flash_erase;
+	flash->internal_read = fast_spi_flash_read;
+	flash->internal_status = fast_spi_flash_status;
+
+	return flash;
+}
+
+int spi_flash_get_fpr_info(struct fpr_info *info)
+{
+	BOILERPLATE_CREATE_CTX(ctx);
+
+	info->base = ctx->mmio_base + SPIBAR_FPR_BASE;
+	info->max = SPIBAR_FPR_MAX;
+	return 0;
+}
+
+/*
+ * Minimal set of commands to read WPSR from FAST_SPI.
+ * Returns 0 on success, < 0 on failure.
+ */
+int fast_spi_flash_read_wpsr(u8 *sr)
+{
+	uint8_t rdsr;
+	int ret = 0;
+
+	fast_spi_init();
+
+	/* sending NULL for spiflash struct parameter since we are not
+	 * calling HWSEQ read_status() call via Probe.
+	 */
+	ret = fast_spi_flash_status(NULL, &rdsr);
+	if (ret) {
+		printk(BIOS_ERR, "SPI rdsr failed\n");
+		return ret;
+	}
+	*sr = rdsr & WPSR_MASK_SRP0_BIT;
+
+	return 0;
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
new file mode 100644
index 0000000000..2b80c49837
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_FAST_SPI_H
+#define SOC_INTEL_COMMON_BLOCK_FAST_SPI_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+/*
+ * Disable the BIOS write protect and Enable Prefetching and Caching.
+ */
+void fast_spi_init(void);
+/*
+ * Minimal set of commands to read WPSR from SPI.
+ * Returns 0 on success, < 0 on failure.
+ */
+int fast_spi_flash_read_wpsr(u8 *sr);
+/*
+ * Set FAST_SPIBAR BIOS Control BILD bit.
+ */
+void fast_spi_set_bios_interface_lock_down(void);
+/*
+ * Set FAST_SPIBAR BIOS Control LE bit.
+ */
+void fast_spi_set_lock_enable(void);
+/*
+ * Set FAST_SPIBAR BIOS Control EISS bit.
+ */
+void fast_spi_set_eiss(void);
+/*
+ * Set FAST_SPI opcode menu.
+ */
+void fast_spi_set_opcode_menu(void);
+/*
+ * Lock FAST_SPIBAR.
+ */
+void fast_spi_lock_bar(void);
+/*
+ * Set FAST_SPIBAR Soft Reset Data Register value.
+ */
+void fast_spi_set_strap_msg_data(uint32_t soft_reset_data);
+/*
+ * Returns bios_start and fills in size of the BIOS region.
+ */
+size_t fast_spi_get_bios_region(size_t *bios_size);
+/*
+ * Program temporary BAR for FAST_SPI in case any of the stages before ramstage
+ * need to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI
+ * enumeration. Also, Disable the BIOS write protect and Enable Prefetching and
+ * Caching.
+ */
+void fast_spi_early_init(uintptr_t spi_base_address);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */