diff options
author | Yuchen He <yuchenhe126@gmail.com> | 2023-07-25 21:28:36 +0200 |
---|---|---|
committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-05 16:04:46 +0000 |
commit | 1e67adbc73e30be098ce163e3d27a7a7ecf68ae0 (patch) | |
tree | a2880851ac6c754d94fc056472beb5ec133ab0b4 /src/soc/intel/common/block | |
parent | 71b8ee0da407158d51eb7d86a6e1d4c458fc8e96 (diff) |
src/*/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 28 | ||||
-rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 2 | ||||
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/post_codes.h | 24 |
3 files changed, 27 insertions, 27 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5f6b6de07c..3c8dc2e686 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -78,7 +78,7 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(POST_BOOTBLOCK_PRE_C_ENTRY) + post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY) /* Bootguard sets up its own CAR and needs separate handling */ check_boot_guard: @@ -98,7 +98,7 @@ no_bootguard: jmp check_mtrr /* Check if CPU properly reset */ no_reset: - post_code(POST_SOC_NO_RESET) + post_code(POSTCODE_SOC_NO_RESET) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list, %ebx @@ -112,7 +112,7 @@ clear_fixed_mtrr: cmp $fixed_mtrr_list_end, %ebx jl clear_fixed_mtrr - post_code(POST_SOC_CLEAR_FIXED_MTRRS) + post_code(POSTCODE_SOC_CLEAR_FIXED_MTRRS) /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx @@ -130,7 +130,7 @@ clear_var_mtrr: dec %ebx jnz clear_var_mtrr - post_code(POST_SOC_CLEAR_VAR_MTRRS) + post_code(POSTCODE_SOC_CLEAR_VAR_MTRRS) /* Configure default memory type to uncacheable (UC) */ mov $MTRR_DEF_TYPE_MSR, %ecx @@ -158,7 +158,7 @@ setup_car_mtrr: bts %eax, %esi dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ - post_code(POST_SOC_SET_UP_CAR_MTRRS) + post_code(POSTCODE_SOC_SET_UP_CAR_MTRRS) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) find_free_mtrr @@ -217,7 +217,7 @@ setup_car_mtrr: #else #error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing" #endif - post_code(POST_SOC_BOOTGUARD_SETUP) + post_code(POSTCODE_SOC_BOOTGUARD_SETUP) is_bootguard_nem jz no_bootguard_car_continue @@ -269,7 +269,7 @@ no_bootguard_car_continue: .global car_init_done car_init_done: - post_code(POST_SOC_CAR_INIT_DONE) + post_code(POSTCODE_SOC_CAR_INIT_DONE) /* Setup bootblock stack */ mov $_ecar_stack, %esp @@ -296,7 +296,7 @@ car_init_done: #endif before_carstage: - post_code(POST_SOC_BEFORE_CARSTAGE) + post_code(POSTCODE_SOC_BEFORE_CARSTAGE) call bootblock_c_entry /* Never reached */ @@ -329,11 +329,11 @@ car_nem: or $0x1, %eax wrmsr - post_code(POST_SOC_CLEARING_CAR) + post_code(POSTCODE_SOC_CLEARING_CAR) clear_car - post_code(POST_SOC_DISABLE_CACHE_EVICT) + post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT) /* Disable cache eviction (run stage) */ mov $MSR_EVICT_CTL, %ecx @@ -418,11 +418,11 @@ car_cqos: and %ebx, %eax wrmsr - post_code(POST_SOC_CLEARING_CAR) + post_code(POSTCODE_SOC_CLEARING_CAR) clear_car - post_code(POST_SOC_DISABLE_CACHE_EVICT) + post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT) /* Cache is populated. Use mask 1 that will block evicts */ mov $IA32_PQR_ASSOC, %ecx @@ -447,7 +447,7 @@ car_nem_enhanced: rdmsr or $0x1, %eax wrmsr - post_code(POST_SOC_CAR_NEM_ENHANCED) + post_code(POSTCODE_SOC_CAR_NEM_ENHANCED) /* Create n-way set associativity of cache */ xorl %edi, %edi @@ -634,7 +634,7 @@ program_sf2: #endif wrmsr - post_code(POST_SOC_DISABLE_CACHE_EVICT) + post_code(POSTCODE_SOC_DISABLE_CACHE_EVICT) /* * Enable No-Eviction Mode Run State by setting * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 14637cedc4..939c793d1a 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -610,7 +610,7 @@ int heci_reset(void) uint32_t csr; /* Clear post code to prevent eventlog entry from unknown code. */ - post_code(POST_CODE_ZERO); + post_code(POSTCODE_CODE_ZERO); /* Send reset request */ csr = read_host_csr(); diff --git a/src/soc/intel/common/block/include/intelblocks/post_codes.h b/src/soc/intel/common/block/include/intelblocks/post_codes.h index 7c78ef8e0e..c4cd2ab04d 100644 --- a/src/soc/intel/common/block/include/intelblocks/post_codes.h +++ b/src/soc/intel/common/block/include/intelblocks/post_codes.h @@ -4,18 +4,18 @@ #define SOC_INTEL_COMMON_BLOCK_POST_CODES_H /* common/block/cpu/car/cache_as_ram.s */ -#define POST_BOOTBLOCK_PRE_C_ENTRY 0x20 -#define POST_SOC_NO_RESET 0x21 -#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 -#define POST_SOC_CLEAR_VAR_MTRRS 0x23 -#define POST_SOC_SET_UP_CAR_MTRRS 0x24 -#define POST_SOC_BOOTGUARD_SETUP 0x25 -#define POST_SOC_CLEARING_CAR 0x26 -#define POST_SOC_DISABLE_CACHE_EVICT 0x27 -#define POST_SOC_CAR_NEM_ENHANCED 0x28 -#define POST_SOC_CAR_INIT_DONE 0x29 -#define POST_SOC_BEFORE_CARSTAGE 0x2a +#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY 0x20 +#define POSTCODE_SOC_NO_RESET 0x21 +#define POSTCODE_SOC_CLEAR_FIXED_MTRRS 0x22 +#define POSTCODE_SOC_CLEAR_VAR_MTRRS 0x23 +#define POSTCODE_SOC_SET_UP_CAR_MTRRS 0x24 +#define POSTCODE_SOC_BOOTGUARD_SETUP 0x25 +#define POSTCODE_SOC_CLEARING_CAR 0x26 +#define POSTCODE_SOC_DISABLE_CACHE_EVICT 0x27 +#define POSTCODE_SOC_CAR_NEM_ENHANCED 0x28 +#define POSTCODE_SOC_CAR_INIT_DONE 0x29 +#define POSTCODE_SOC_BEFORE_CARSTAGE 0x2a /* common/block/cse/cse.c */ -#define POST_CODE_ZERO 0x00 +#define POSTCODE_CODE_ZERO 0x00 #endif |