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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-25 14:51:50 +0200 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-06-02 15:58:34 +0000 |
| commit | 0024678d17586aa294684e2b27acf5c04b22fb08 (patch) | |
| tree | 6637a4d363ccedb0234d3aec4389f602281fe31d /src/soc/intel/common/block | |
| parent | 346db92f8c6e42529af6dbcf34caf9c3fb1a5a12 (diff) | |
cpu/intel/model_fxx: Select SSE2
Starting from Intel Pentium 4, cpus featured SSE2.
This will be used in the follow-up patches to determine whether to use
mfence as this instruction was introduced with the SSE2 feature set.
Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block')
0 files changed, 0 insertions, 0 deletions