soc/intel: Move soc_pch_pirq_init() to common code

List of changes:
1. Rename soc_pch_pirq_init() as pch_pirq_init() and
move into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.

TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.

Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

2 files changed, 72 insertions, 3 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 5bbc384e82..52b0ff8e72 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -97,8 +97,6 @@ void lpc_disable_clkrun(void);
 void lpc_io_setup_comm_a_b(void);
 /* Enable PCH LPC by setting up generic decode range registers. */
 void pch_enable_lpc(void);
-/* Retrieve and setup SoC specific PCH LPC interrupt routing. */
-void soc_pch_pirq_init(const struct device *dev);
 /* Get SoC's generic IO decoder range register settings. */
 void soc_get_gen_io_dec_range(const struct device *dev,
 			uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]);
@@ -109,5 +107,7 @@ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
 	uintptr_t base, size_t size, unsigned long flags);
 /* Enable PCH IOAPIC */
 void pch_enable_ioapic(void);
+/* Retrieve and setup PCH LPC interrupt routing. */
+void pch_pirq_init(void);
 
 #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 87ee11056e..d189a5e398 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -7,9 +7,11 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
+#include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
 #include <lib.h>
 #include "lpc_def.h"
+#include <soc/irq.h>
 #include <soc/pci_devs.h>
 
 uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
@@ -280,7 +282,7 @@ void pch_enable_lpc(void)
 	lpc_set_gen_decode_range(gen_io_dec);
 	soc_setup_dmi_pcr_io_dec(gen_io_dec);
 	if (ENV_PAYLOAD_LOADER)
-		soc_pch_pirq_init(dev);
+		pch_pirq_init();
 }
 
 void lpc_enable_pci_clk_cntl(void)
@@ -317,3 +319,70 @@ void pch_enable_ioapic(void)
 	 */
 	io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
 }
+
+/*
+ * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+void pch_pirq_init(void)
+{
+	const struct device *irq_dev;
+	uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
+
+	pch_interrupt_routing[0] = PCH_IRQ11;
+	pch_interrupt_routing[1] = PCH_IRQ10;
+	pch_interrupt_routing[2] = PCH_IRQ11;
+	pch_interrupt_routing[3] = PCH_IRQ11;
+	pch_interrupt_routing[4] = PCH_IRQ11;
+	pch_interrupt_routing[5] = PCH_IRQ11;
+	pch_interrupt_routing[6] = PCH_IRQ11;
+	pch_interrupt_routing[7] = PCH_IRQ11;
+
+	itss_irq_init(pch_interrupt_routing);
+
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+		uint8_t int_pin = 0, int_line = 0;
+
+		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+			continue;
+
+		int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN);
+
+		switch (int_pin) {
+		case 1: /* INTA# */
+			int_line = PCH_IRQ11;
+			break;
+		case 2: /* INTB# */
+			int_line = PCH_IRQ10;
+			break;
+		case 3: /* INTC# */
+			int_line = PCH_IRQ11;
+			break;
+		case 4: /* INTD# */
+			int_line = PCH_IRQ11;
+			break;
+		}
+
+		if (!int_line)
+			continue;
+
+		pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line);
+	}
+}