diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-10 09:24:54 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-04-10 18:07:54 +0000 |
| commit | 551e4be7301eca04104c8f0d4379b906dfb07c1b (patch) | |
| tree | 5d7183a8863fadfe1ff2f1a4c556c9ae69e3419d /src/soc/intel/common/block | |
| parent | 6d61db0d2cec4a3b141da77bcf5675b8b154c8b7 (diff) | |
soc/intel/common: prepare for lpss clock split
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/gspi/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/gspi/gspi.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/lpss.h | 4 |
3 files changed, 12 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/gspi/Kconfig b/src/soc/intel/common/block/gspi/Kconfig index 8fa847a1b8..d2776ca1a4 100644 --- a/src/soc/intel/common/block/gspi/Kconfig +++ b/src/soc/intel/common/block/gspi/Kconfig @@ -3,6 +3,14 @@ config SOC_INTEL_COMMON_BLOCK_GSPI help Intel Processor Common GSPI support +config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ + int + depends on SOC_INTEL_COMMON_BLOCK_GSPI + help + The input clock speed into the SPI controller IP block, in MHz. + No default is set here as this is an SOC-specific value + and must be provided by the SOC. + config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int depends on SOC_INTEL_COMMON_BLOCK_GSPI diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 60c7391ad0..e4e44c22bb 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -380,7 +380,8 @@ static void gspi_cs_deassert(const struct spi_slave *dev) static uint32_t gspi_get_clk_div(unsigned int gspi_bus) { - const uint32_t ref_clk_mhz = CONFIG_SOC_INTEL_COMMON_LPSS_CLOCK_MHZ; + const uint32_t ref_clk_mhz = + CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ; const uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus); assert(gspi_clk_mhz != 0); diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index c6caae2675..ca5568996f 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -22,8 +22,8 @@ void lpss_reset_release(uintptr_t base); /* - * Update clock divider parameters. Clock frequency is - * configured as SOC_INTEL_COMMON_LPSS_CLOCK_MHZ * (M / N) + * Update clock divider parameters. Clock frequency is dependent on source + * clock frequency of each IP block. Resulting clock will be src_freq * (M / N). */ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); |