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authorJohn Zhao <john.zhao@intel.com>2019-05-21 19:32:51 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-05-29 20:08:04 +0000
commit2bb432ece634af05aade44ea55755ae3e6637acf (patch)
treea1391ea84010f27292d4230d12f98e9a4a4b2734 /src/soc/intel/common/block
parent64fb5aa9c3e50a49d2ecc153ff8c597e203475bc (diff)
soc/intel/common: Check bios_size and window_size after MIN operation
Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size) and log2_ceil(window_size) are garbage or undefined if the value of bios_size and window_size is zero. Check bios_size and window_size after MIN operation to prevent error. TEST=Built and boot up to kernel. Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/fast_spi/fast_spi.c5
-rw-r--r--src/soc/intel/common/block/lpc/lpc_lib.c3
2 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 455b13ccb7..58e7db75a1 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -236,14 +236,13 @@ void fast_spi_cache_bios_region(void)
/* Only the IFD BIOS region is memory mapped (at top of 4G) */
fast_spi_get_bios_region(&bios_size);
- if (!bios_size)
- return;
-
/* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will
* cause memory type conflict when setting memory type to write
* protection, so limit the cached bios region to be no more than 16MB.
* */
bios_size = MIN(bios_size, 16 * MiB);
+ if (!bios_size)
+ return;
/* Round to power of two */
alignment = 1UL << (log2_ceil(bios_size));
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index b383637736..c67c43532c 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -80,6 +80,9 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size)
/* Each IO range register can only open a 256-byte window. */
window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE);
+ if (!window_size)
+ return;
+
/* Window size must be a power of two for the AMASK to work. */
alignment = 1UL << (log2_ceil(window_size));
window_size = ALIGN_UP(window_size, alignment);