diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-29 13:55:50 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-03 04:18:32 +0000 |
| commit | 1366e4438d07c2de905454421e18d1e5f68de47d (patch) | |
| tree | eebb4803b4e0ebada8372d3482fa2d5ae3c93b6f /src/soc/intel/common/block | |
| parent | 18b1984f8666fbbac40b08c8de86cef15a9d9a9b (diff) | |
soc/intel: Move pch_enable_ioapic() to common code
List of changes:
1. Move pch_enable_ioapic() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpc/lpc_lib.c | 25 |
2 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index ff4ba1ad05..5bbc384e82 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -107,5 +107,7 @@ void soc_setup_dmi_pcr_io_dec(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]); /* Add resource into LPC PCI device space */ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags); +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index ff44cc1a67..87ee11056e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -2,6 +2,7 @@ #define __SIMPLE_DEVICE__ +#include <arch/ioapic.h> #include <assert.h> #include <console/console.h> #include <device/pci.h> @@ -292,3 +293,27 @@ void lpc_disable_clkrun(void) const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); } + +/* Enable PCH IOAPIC */ +void pch_enable_ioapic(void) +{ + uint32_t reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} |