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| author | Furquan Shaikh <furquan@chromium.org> | 2017-08-04 16:24:12 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-08-10 16:25:10 +0000 |
| commit | 96024836077d28100035950e517b2ae5ad1ab5d9 (patch) | |
| tree | 78fd702432075acdde0b5ab895f304d51738b5a0 /src/soc/intel/common/block | |
| parent | a8198eb9ad1daea7b88ffa1d995907783a7c13c3 (diff) | |
soc/intel/skylake: Enable UART debug controller on S3 resume
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.
BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: coreboot skips
initialization of debug controller on S3 resume.
Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
0 files changed, 0 insertions, 0 deletions