diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-13 22:58:28 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-16 22:20:47 +0000 |
| commit | 90df9166834f26a7600d089bc2fade0f34fd6681 (patch) | |
| tree | 19123d60f02b305111e513c262952f0f9a379705 /src/soc/intel/common/block | |
| parent | d32bb116f063d04e0c5f72e6fd0367d6e542c9fb (diff) | |
include/cpu/x86: introduce new helper for (un)setting MSRs
msr_set_bit can only set single bits in MSRs and causes mixing of bit
positions and bitmasks in the MSR header files. Thus, replace the helper
by versions which can unset and set whole MSR bitmasks, just like the
"and-or"-helper, but in the way commit 64a6b6c was done (inversion done
in the helper). This helps keeping the MSR macros unified in bitmask
style.
In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get
added.
The few uses of msr_set_bit have been replaced by the new version, while
the used macros have been converted accordingly.
Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index cbf9b1b9dd..9092df1796 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -337,7 +337,7 @@ void mca_configure(void) void cpu_lt_lock_memory(void *unused) { - msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); + msr_set(MSR_LT_CONTROL, LT_CONTROL_LOCK); } int get_valid_prmrr_size(void) diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 4aa069e068..2ef4561341 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -56,7 +56,7 @@ #define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 #define MSR_LT_CONTROL 0x2e7 -#define LT_CONTROL_LOCK_BIT (0) +#define LT_CONTROL_LOCK (1 << 0) #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define SMM_FEATURE_CONTROL_MSR 0x4e0 |