diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-01 00:11:29 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 17:21:10 +0000 |
| commit | 7c31d17317596c766ac15350560d76035cc8ef08 (patch) | |
| tree | f0100d9fab8facd87d649cdfa6d47bed739402d4 /src/soc/intel/common/block | |
| parent | b3671ec5de62f9c15ee74a8134b4a711cc785886 (diff) | |
soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
This patch creates a global function `cse_send_end_of_post()` so
that IA common code may get access to this function for sending EOP
command to the HECI1/CSE device.
Additionally, use static variable to track and prevent sending EOP
command more than once in boot flow.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_eop.c | 21 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 3 |
2 files changed, 23 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 5d6a4a7886..c17e2278f2 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -185,8 +185,15 @@ static void handle_cse_eop_result(enum cse_eop_result result) } } -static void set_cse_end_of_post(void *unused) +static void do_send_end_of_post(void) { + static bool eop_sent = false; + + if (eop_sent) { + printk(BIOS_ERR, "EOP already sent\n"); + return; + } + /* * If CSE is already hidden then accessing CSE registers would be wrong and will * receive junk, hence, return as CSE is already disabled. @@ -203,6 +210,18 @@ static void set_cse_end_of_post(void *unused) timestamp_add_now(TS_ME_AFTER_END_OF_POST); set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); + + eop_sent = true; +} + +void cse_send_end_of_post(void) +{ + return do_send_end_of_post(); +} + +static void set_cse_end_of_post(void *unused) +{ + return do_send_end_of_post(); } /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index e67d9d8469..f031ad5105 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -498,6 +498,9 @@ void heci_set_to_d0i3(void); /* Function performs the global reset lock */ void cse_control_global_reset_lock(void); +/* Send End of Post (EOP) command to CSE device */ +void cse_send_end_of_post(void); + /* * SoC override API to make heci1 disable using PCR. * |