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authorSubrata Banik <subratabanik@google.com>2022-03-15 18:29:33 +0530
committerSubrata Banik <subratabanik@google.com>2022-03-17 06:02:04 +0000
commit73ad818bc9222aea695e0e8e5ffe53c20633a33f (patch)
tree0f34c03841b8b22e681e1b56667a516dd41d8e83 /src/soc/intel/common/block
parent1f28c853de084c88c42058ac6939db6de659101f (diff)
soc/intel/common/block/cpu: Enable ROM caching in ramstage
Cache the BIOS region and extended BIOS region if the boot device is memory mapped, which is mostly the case with Intel SoC platform. Having the ROM region cached helped to improve the pre-boot time. TEST=Able to boot redrix to Chrome OS without seeing any sluggishness. Additionally verified on EHL board (from siemens), shows significant savings in payload loading time as below: Here is the timestamp snippet showing the payload load time as a comparison between current upstream and the patched version: upstream: 90:starting to load payload 1,072,459 (1,802) 958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619) with this patch: 90:starting to load payload 1,072,663 (2,627) 958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/cpu/mp_init.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 99d9507c55..2d838c5ea3 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -152,6 +152,14 @@ static void coreboot_init_cpus(void *unused)
init_cpus();
}
+static void post_cpus_add_romcache(void)
+{
+ if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
+ return;
+
+ fast_spi_cache_bios_region();
+}
+
static void wrapper_x86_setup_mtrrs(void *unused)
{
x86_setup_mtrrs_with_detect();
@@ -163,6 +171,7 @@ static void post_cpus_init(void *unused)
if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS)
printk(BIOS_ERR, "MTRR programming failure\n");
+ post_cpus_add_romcache();
x86_mtrr_check();
}