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authorKevin Chang <kevin.chang@lcfc.corp-partner.google.com>2022-03-18 21:04:07 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-03-22 05:01:57 +0000
commit6e52c1da4a2245a7499530ea0943fa002ed8aa5e (patch)
tree622f2b388eaa2f85136c747191dd4b1462080327 /src/soc/intel/common/block
parent4b1f25d82f2c5837172446073f4431ca5e0242e1 (diff)
soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
This change provides config for devicetree to control ASPM per port BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles on taeko. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919 Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin L Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pcie_rp.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 2f3b83ce4c..66ced7ee46 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -42,6 +42,16 @@ enum L1_substates_control {
L1_SS_L1_2,
};
+/* This enum is for passing into an FSP UPD, typically ASPM */
+enum ASPM_control {
+ ASPM_DEFAULT,
+ ASPM_DISABLE,
+ ASPM_L0S,
+ ASPM_L1,
+ ASPM_L0S_L1,
+ ASPM_AUTO,
+};
+
/* PCIe Root Ports */
struct pcie_rp_config {
/* CLKOUT_PCIE_P/N# used by this root port as per schematics. */
@@ -51,6 +61,8 @@ struct pcie_rp_config {
enum pcie_rp_flags flags;
/* PCIe RP L1 substate */
enum L1_substates_control PcieRpL1Substates;
+ /* PCIe RP ASPM */
+ enum ASPM_control pcie_rp_aspm;
};
/*