soc/intel/graphics: Repurpose graphics_get_memory_base()

create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.

BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.

Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61389
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 17 insertions, 8 deletions

diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig
index 1ec074e9cd..bc07f5626f 100644
--- a/src/soc/intel/common/block/graphics/Kconfig
+++ b/src/soc/intel/common/block/graphics/Kconfig
@@ -19,4 +19,14 @@ config SOC_INTEL_DISABLE_IGD
 	  where OS can only use one GPU hence need to disable IGD and don't
 	  need to run FSP GOP.
 
+config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET
+	hex
+	default 0x0
+	help
+	  PCI config offset 0x18 point to LMEMBAR and need to add GTT size to
+	  reach at DSM which is referred here as SOC_INTEL_GFX_MEMBASE_OFFSET.
+	  SoC that follow such design would override SOC_INTEL_GFX_FRAMEBUFFER_OFFSET
+	  with GTT_SIZE value. On SoC platform where PCI config offset 0x18 points
+	  to the GMADR directly can use the default value 0x0 without any override.
+
 endif
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 4b0b4c4b87..6118f9960f 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -59,7 +59,7 @@ static void gma_init(struct device *const dev)
 	 */
 	if (CONFIG(RUN_FSP_GOP)) {
 		const struct soc_intel_common_config *config = chip_get_common_soc_structure();
-		fsp_report_framebuffer_info(graphics_get_memory_base(),
+		fsp_report_framebuffer_info(graphics_get_framebuffer_address(),
 					    config->panel_orientation);
 		return;
 	}
@@ -107,21 +107,20 @@ static uintptr_t graphics_get_bar(struct device *dev, unsigned long index)
 	return gm_res->base;
 }
 
-uintptr_t graphics_get_memory_base(void)
+uintptr_t graphics_get_framebuffer_address(void)
 {
 	uintptr_t memory_base;
 	struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
 
 	if (is_graphics_disabled(dev))
 		return 0;
-	/*
-	 * GFX PCI config space offset 0x18 know as Graphics
-	 * Memory Range Address (GMADR)
-	 */
+
 	memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
 	if (!memory_base)
 		die_with_post_code(POST_HW_INIT_FAILURE,
-				   "GMADR is not programmed!");
+				   "Graphic memory bar2 is not programmed!");
+
+	memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET;
 
 	return memory_base;
 }
diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h
index 3669c7733d..63aa800dce 100644
--- a/src/soc/intel/common/block/include/intelblocks/graphics.h
+++ b/src/soc/intel/common/block/include/intelblocks/graphics.h
@@ -26,6 +26,6 @@ intel_igd_get_controller_info(const struct device *device);
 uint32_t graphics_gtt_read(unsigned long reg);
 void graphics_gtt_write(unsigned long reg, uint32_t data);
 void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask);
-uintptr_t graphics_get_memory_base(void);
+uintptr_t graphics_get_framebuffer_address(void);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */