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authorMAULIK V VAGHELA <maulik.v.vaghela@intel.com>2021-12-17 17:55:22 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-03-10 15:15:38 +0000
commit61b8f89ce3765b01cdecbcd86cbfe4438bfeba51 (patch)
treec935444c0c21e33c75c18d218aaffe6590dece1e /src/soc/intel/common/block
parent40ca79714ad7d5f2aa201d83db4d97f21260d924 (diff)
intel/common/block/cse: Add option to send EOP early via SoC
Earlier while trying to optimize boot time End Of Post (EOP) time kept increasing (~80 ms) when boot time decreased to around 1 second. This was because CSE was busy with own firmware loading. When EOP was moved later in boot stage it again created issue since CSE got busy with other payload loading for OS boot, so response to EOP got delayed by ~70-80 ms. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board. Since this setting might vary for each SoC, SoCs can decide when to send EOP in the boot sequence. This patch adds Kconfig option to send EOP via SoC BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Code compilation is fine for Brya board. Boot time test is done using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms. Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/common/block')
-rw-r--r--src/soc/intel/common/block/cse/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index fb7548676e..e30244799e 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -45,6 +45,15 @@ config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented)
to make `HECI1` device disable using private configuration register (PCR) write.
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+ bool
+ depends on SOC_INTEL_COMMON_BLOCK_CSE
+ help
+ Use this config to send End Of Post (EOP) earlier through SoC code in order to
+ reduce time required to send EOP and getting CSE response.
+ In later stages, CSE might be busy and might require more time to process EOP command.
+ SoC can use this Kconfig to send EOP earlier by itself.
+
config SOC_INTEL_CSE_LITE_SKU
bool
default n