soc/intel/common: Add support for LPSS UART in ACPI mode

Emit ACPI code for LPSS UARTs operating in ACPI mode. In this mode the
device vendor ID reads as 0xffff, the PCI devices is still operate.

Add ACPI device IDs for APL, GLK, SPT, SPT_H and CNP_H.

The mainboard's devicetree needs to be adapted to include the chip
driver and the PCI ID when it wouldn't have been hidden.

Example:
 chip soc/intel/common/block/uart
  device pci 19.2 hidden
   register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
  end # UART #2
 end

Tested on Linux 5.6 with Sunrise Point ACPI ID for UART2.
Tested on Windows for all other UARTs.

Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 15 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/uart/chip.h b/src/soc/intel/common/block/uart/chip.h
new file mode 100644
index 0000000000..5981126fa9
--- /dev/null
+++ b/src/soc/intel/common/block/uart/chip.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+/* Indirect include for static.c: */
+#include <device/pci_ids.h>
+
+#ifndef _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_
+#define _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_
+
+struct soc_intel_common_block_uart_config {
+	/* The Device ID read from config space at offset[2:4] when not hidden */
+	u16 devid;
+};
+
+#endif /* _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ */