diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2017-05-25 13:49:53 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-05 00:30:31 +0200 |
| commit | 1fa16c9cb6c486cdd4b1bcb3734308b28b9c9a22 (patch) | |
| tree | 3d29cd870fbf8345020361e70f3f19bd9c6b53bd /src/soc/intel/common/block/timer/Makefile.inc | |
| parent | 22b2c793e3587fb98d42f88e5e623621e055ff3a (diff) | |
soc/intel/common: Add common Intel timer code
Add common timer code to get tsc frequency(Mhz).
Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/timer/Makefile.inc')
| -rw-r--r-- | src/soc/intel/common/block/timer/Makefile.inc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/timer/Makefile.inc b/src/soc/intel/common/block/timer/Makefile.inc new file mode 100644 index 0000000000..b562c50781 --- /dev/null +++ b/src/soc/intel/common/block/timer/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c |