diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-01-03 15:29:02 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-10 08:40:57 +0000 |
| commit | b6df6b065cffea9b93f6fdbd041ee15e4ec6fd61 (patch) | |
| tree | 48969f4662f0f458deb8cb47abd321559ff64ee9 /src/soc/intel/common/block/systemagent/systemagent.c | |
| parent | 1c3086a6036f9908c8c09c823c5ad1718eac7ce0 (diff) | |
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource
if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size
is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref]
[ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref]
[ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/systemagent/systemagent.c')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent.c | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 2da3992ca4..0fab7d9619 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2020 Intel Corporation. * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify @@ -14,12 +14,13 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/acpi.h> +#include <intelblocks/cfg.h> #include <intelblocks/systemagent.h> #include <smbios.h> #include <soc/iomap.h> @@ -54,6 +55,34 @@ __weak unsigned long sa_write_acpi_tables(struct device *dev, } /* + * This function will get above 4GB mmio enable config specific to soc. + * + * Return values: + * 0 = Above 4GB memory is not enable + * 1 = Above 4GB memory is enable + */ +static int get_enable_above_4GB_mmio(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->enable_above_4GB_mmio; +} + +/* Fill MMIO resource above 4GB into GNVS */ +void sa_fill_gnvs(global_nvs_t *gnvs) +{ + if (get_enable_above_4GB_mmio()) { + gnvs->e4gm = 1; + gnvs->a4gb = ABOVE_4GB_MEM_BASE_ADDRESS; + gnvs->a4gs = ABOVE_4GB_MEM_BASE_SIZE; + printk(BIOS_DEBUG, + "PCI space above 4GB MMIO is from 0x%llx to len = 0x%llx\n", + gnvs->a4gb, gnvs->a4gs); + } +} + +/* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ |