diff options
author | Kane Chen <kane.chen@intel.com> | 2017-10-16 19:40:18 +0800 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-31 15:49:55 +0000 |
commit | 66f1f382cd3bd5a7250e0a7ad35d9a1c505de47a (patch) | |
tree | 899e5780ab5d63b9e8d4a6d9402fe0d3f8f4c9e8 /src/soc/intel/common/block/smbus/smbuslib.c | |
parent | dfd2a8b7e7bba6ccffb141f812f70b5bc608f37a (diff) |
intel/common/smbus: increase spd read performance
This change increases the spd read performance by using smbus word
access.
BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement on one dimm
Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/smbus/smbuslib.c')
-rw-r--r-- | src/soc/intel/common/block/smbus/smbuslib.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 27b4ad5c5d..0d3901fa2b 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -135,3 +135,44 @@ int smbus_write8(unsigned int smbus_base, unsigned int device, return 0; } + +int smbus_read16(unsigned int smbus_base, unsigned int device, + unsigned int address) +{ + unsigned char global_status_register; + unsigned short data; + + if (smbus_wait_till_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Set up transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & ~1, smbus_base + SMBHSTCTL); + /* Set the device I'm talking to */ + outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a word data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x3 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_till_done(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + + global_status_register = inb(smbus_base + SMBHSTSTAT); + /* Ignore the "In Use" status... */ + if ((global_status_register & ~(3 << 5)) != (1 << 1)) + return SMBUS_ERROR; + + /* Read results of transaction */ + data = inw(smbus_base + SMBHSTDAT0); + + return data; +} |