diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-28 17:50:00 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-03 06:57:51 +0000 |
| commit | 3e959d8e2a05a50ca16430dcacfd4794db1e49fc (patch) | |
| tree | 6c5bb300d054947906bde2351f345fe134238329 /src/soc/intel/common/block/pmc/Kconfig | |
| parent | 8971ccd576a7b0edbd02101b0c3bc3541cb6a741 (diff) | |
soc/intel/common/block/pmc: Add PMC API for low power programming
List of changes:
1. Create Kconfig to select pmc low power program by SoC
2. Add API to make ACPI timer disable
3. Add API to ignore XTAL shutdown for SLP_S0# assertion
Change-Id: I017ddc772f02ccba889d316319ab3d5626b80ba5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/pmc/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/pmc/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 3aa0da8b1e..ce41b23620 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -29,3 +29,9 @@ config PMC_GLOBAL_RESET_ENABLE_LOCK and lock register is located under PMC BASE at offset ETR. Note that the reset register is still at 0xCF9 this only controls the enable and lock feature. + +config PMC_LOW_POWER_MODE_PROGRAM + bool + help + Enable this for PMC devices to perform registers programming + to ensure low power in active idle scenario. |