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authorAamir Bohra <aamir.bohra@intel.com>2017-04-06 11:10:35 +0530
committerMartin Roth <martinroth@google.com>2017-04-10 20:46:17 +0200
commit237a93c43e9d269926f34839ee88f00833701ce6 (patch)
tree47fc3781b00af8ae979942e2c326f77045214366 /src/soc/intel/common/block/lpss/Makefile.inc
parent8bf69d307892c65cdc604136146c1a6702956e20 (diff)
soc/intel/common/block: Add LPSS function library
LPSS function library implements common register programming under lpss. Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block/lpss/Makefile.inc')
-rw-r--r--src/soc/intel/common/block/lpss/Makefile.inc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc
new file mode 100644
index 0000000000..6c56c6831e
--- /dev/null
+++ b/src/soc/intel/common/block/lpss/Makefile.inc
@@ -0,0 +1,3 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c \ No newline at end of file